StateMachine.py (6793:bc8c8617c4f0) StateMachine.py (6862:3d308cbd1657)
1# Copyright (c) 1999-2008 Mark D. Hill and David A. Wood
2# Copyright (c) 2009 The Hewlett-Packard Development Company
3# All rights reserved.
4#
5# Redistribution and use in source and binary forms, with or without
6# modification, are permitted provided that the following conditions are
7# met: redistributions of source code must retain the above copyright
8# notice, this list of conditions and the following disclaimer;

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181 const int & getVersion() const;
182 const string toString() const;
183 const string getName() const;
184 const MachineType getMachineType() const;
185 void print(ostream& out) const;
186 void printConfig(ostream& out) const;
187 void wakeup();
188 void set_atomic(Address addr);
1# Copyright (c) 1999-2008 Mark D. Hill and David A. Wood
2# Copyright (c) 2009 The Hewlett-Packard Development Company
3# All rights reserved.
4#
5# Redistribution and use in source and binary forms, with or without
6# modification, are permitted provided that the following conditions are
7# met: redistributions of source code must retain the above copyright
8# notice, this list of conditions and the following disclaimer;

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181 const int & getVersion() const;
182 const string toString() const;
183 const string getName() const;
184 const MachineType getMachineType() const;
185 void print(ostream& out) const;
186 void printConfig(ostream& out) const;
187 void wakeup();
188 void set_atomic(Address addr);
189 void started_writes();
190 void clear_atomic();
189 void clear_atomic(Address addr);
190 void reset_atomics();
191 void printStats(ostream& out) const { s_profiler.dumpStats(out); }
192 void clearStats() { s_profiler.clearStats(); }
193private:
194''')
195
196 code.indent()
197 # added by SS
198 for param in self.config_parameters:
199 code('int m_${{param.ident}};')
200
201 if self.ident == "L1Cache":
202 code('''
203int servicing_atomic;
191 void printStats(ostream& out) const { s_profiler.dumpStats(out); }
192 void clearStats() { s_profiler.clearStats(); }
193private:
194''')
195
196 code.indent()
197 # added by SS
198 for param in self.config_parameters:
199 code('int m_${{param.ident}};')
200
201 if self.ident == "L1Cache":
202 code('''
203int servicing_atomic;
204bool started_receiving_writes;
205Address locked_read_request1;
206Address locked_read_request2;
207Address locked_read_request3;
208Address locked_read_request4;
209int read_counter;
210''')
211
212 code('''

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296$c_ident::$c_ident(const string &name)
297 : m_name(name)
298{
299''')
300 code.indent()
301 if self.ident == "L1Cache":
302 code('''
303servicing_atomic = 0;
204Address locked_read_request1;
205Address locked_read_request2;
206Address locked_read_request3;
207Address locked_read_request4;
208int read_counter;
209''')
210
211 code('''

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295$c_ident::$c_ident(const string &name)
296 : m_name(name)
297{
298''')
299 code.indent()
300 if self.ident == "L1Cache":
301 code('''
302servicing_atomic = 0;
304started_receiving_writes = false;
305locked_read_request1 = Address(-1);
306locked_read_request2 = Address(-1);
307locked_read_request3 = Address(-1);
308locked_read_request4 = Address(-1);
309read_counter = 0;
310''')
311
312 code('m_num_controllers++;')

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595
596 assert mandatory_q is not None
597
598 # print out the mandatory queue here
599 port = mandatory_q
600 code('// ${ident}InPort $port')
601 output = port["c_code_in_port"]
602
303locked_read_request1 = Address(-1);
304locked_read_request2 = Address(-1);
305locked_read_request3 = Address(-1);
306locked_read_request4 = Address(-1);
307read_counter = 0;
308''')
309
310 code('m_num_controllers++;')

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593
594 assert mandatory_q is not None
595
596 # print out the mandatory queue here
597 port = mandatory_q
598 code('// ${ident}InPort $port')
599 output = port["c_code_in_port"]
600
603 pos = output.find("TransitionResult result = doTransition((L1Cache_mandatory_request_type_to_event(((*in_msg_ptr)).m_Type)), L1Cache_getState(addr), addr);")
604 assert pos >= 0
605 atomics_string = '''
606if ((((*in_msg_ptr)).m_Type) == CacheRequestType_ATOMIC) {
607 if (servicing_atomic == 0) {
608 if (locked_read_request1 == Address(-1)) {
609 assert(read_counter == 0);
610 locked_read_request1 = addr;
611 assert(read_counter == 0);
612 read_counter++;
613 }
614 else if (addr == locked_read_request1) {
615 ; // do nothing
616 }
617 else {
618 assert(0); // should never be here if servicing one request at a time
619 }
620 }
621 else if (!started_receiving_writes) {
622 if (servicing_atomic == 1) {
623 if (locked_read_request2 == Address(-1)) {
624 assert(locked_read_request1 != Address(-1));
625 assert(read_counter == 1);
626 locked_read_request2 = addr;
627 assert(read_counter == 1);
628 read_counter++;
629 }
630 else if (addr == locked_read_request2) {
631 ; // do nothing
632 }
633 else {
634 assert(0); // should never be here if servicing one request at a time
635 }
636 }
637 else if (servicing_atomic == 2) {
638 if (locked_read_request3 == Address(-1)) {
639 assert(locked_read_request1 != Address(-1));
640 assert(locked_read_request2 != Address(-1));
641 assert(read_counter == 1);
642 locked_read_request3 = addr;
643 assert(read_counter == 2);
644 read_counter++;
645 }
646 else if (addr == locked_read_request3) {
647 ; // do nothing
648 }
649 else {
650 assert(0); // should never be here if servicing one request at a time
651 }
652 }
653 else if (servicing_atomic == 3) {
654 if (locked_read_request4 == Address(-1)) {
655 assert(locked_read_request1 != Address(-1));
656 assert(locked_read_request2 != Address(-1));
657 assert(locked_read_request3 != Address(-1));
658 assert(read_counter == 1);
659 locked_read_request4 = addr;
660 assert(read_counter == 3);
661 read_counter++;
662 }
663 else if (addr == locked_read_request4) {
664 ; // do nothing
665 }
666 else {
667 assert(0); // should never be here if servicing one request at a time
668 }
669 }
670 else {
671 assert(0);
672 }
673 }
674}
675else {
676 if (servicing_atomic > 0) {
677 // reset
678 servicing_atomic = 0;
679 read_counter = 0;
680 started_receiving_writes = false;
681 locked_read_request1 = Address(-1);
682 locked_read_request2 = Address(-1);
683 locked_read_request3 = Address(-1);
684 locked_read_request4 = Address(-1);
685 }
686}
687'''
688
689 output = output[:pos] + atomics_string + output[pos:]
690 code('$output')
691
692 for port in self.in_ports:
693 # don't print out mandatory queue twice
694 if port == mandatory_q:
695 continue
696
697 if ident == "L1Cache":
601 code('$output')
602
603 for port in self.in_ports:
604 # don't print out mandatory queue twice
605 if port == mandatory_q:
606 continue
607
608 if ident == "L1Cache":
698 if str(port).find("forwardRequestNetwork_in") >= 0:
609 if (str(port).find("forwardRequestNetwork_in") >= 0 or str(port).find("requestNetwork_in") >= 0 or str(port).find("requestIntraChipL1Network_in") >= 0):
699 code('''
700bool postpone = false;
701if ((((*m_L1Cache_forwardToCache_ptr)).isReady())) {
702 const RequestMsg* in_msg_ptr;
703 in_msg_ptr = dynamic_cast<const RequestMsg*>(((*m_L1Cache_forwardToCache_ptr)).peek());
610 code('''
611bool postpone = false;
612if ((((*m_L1Cache_forwardToCache_ptr)).isReady())) {
613 const RequestMsg* in_msg_ptr;
614 in_msg_ptr = dynamic_cast<const RequestMsg*>(((*m_L1Cache_forwardToCache_ptr)).peek());
704 if ((((servicing_atomic == 1) && (locked_read_request1 == ((*in_msg_ptr)).m_Address)) ||
705 ((servicing_atomic == 2) && (locked_read_request1 == ((*in_msg_ptr)).m_Address || locked_read_request2 == ((*in_msg_ptr)).m_Address)) ||
706 ((servicing_atomic == 3) && (locked_read_request1 == ((*in_msg_ptr)).m_Address || locked_read_request2 == ((*in_msg_ptr)).m_Address || locked_read_request3 == ((*in_msg_ptr)).m_Address)) ||
707 ((servicing_atomic == 4) && (locked_read_request1 == ((*in_msg_ptr)).m_Address || locked_read_request2 == ((*in_msg_ptr)).m_Address || locked_read_request3 == ((*in_msg_ptr)).m_Address || locked_read_request1 == ((*in_msg_ptr)).m_Address)))) {
708 postpone = true;
615 if ((((servicing_atomic > 0) && (locked_read_request1 == ((*in_msg_ptr)).m_Address || locked_read_request2 == ((*in_msg_ptr)).m_Address || locked_read_request3 == ((*in_msg_ptr)).m_Address || locked_read_request1 == ((*in_msg_ptr)).m_Address)))) {
616 postpone = true;
709 }
710}
711if (!postpone) {
712''')
713 code.indent()
714 code('// ${ident}InPort $port')
715 code('${{port["c_code_in_port"]}}')
716 code.dedent()
717
718 if ident == "L1Cache":
617 }
618}
619if (!postpone) {
620''')
621 code.indent()
622 code('// ${ident}InPort $port')
623 code('${{port["c_code_in_port"]}}')
624 code.dedent()
625
626 if ident == "L1Cache":
719 if str(port).find("forwardRequestNetwork_in") >= 0:
627 if (str(port).find("forwardRequestNetwork_in") >= 0 or str(port).find("requestNetwork_in") >= 0 or str(port).find("requestIntraChipL1Network_in") >= 0):
720 code.dedent()
721 code('}')
722 code.indent()
723 code('')
724
725 code.dedent()
726 code.dedent()
727 code('''
728 break; // If we got this far, we have nothing left todo
729 }
730}
731''')
732
733 if self.ident == "L1Cache":
734 code('''
735void ${ident}_Controller::set_atomic(Address addr)
736{
737 servicing_atomic++;
628 code.dedent()
629 code('}')
630 code.indent()
631 code('')
632
633 code.dedent()
634 code.dedent()
635 code('''
636 break; // If we got this far, we have nothing left todo
637 }
638}
639''')
640
641 if self.ident == "L1Cache":
642 code('''
643void ${ident}_Controller::set_atomic(Address addr)
644{
645 servicing_atomic++;
646 switch (servicing_atomic) {
647 case(1):
648 assert(locked_read_request1 == Address(-1));
649 locked_read_request1 = addr;
650 break;
651 case(2):
652 assert(locked_read_request2 == Address(-1));
653 locked_read_request2 = addr;
654 break;
655 case(3):
656 assert(locked_read_request3 == Address(-1));
657 locked_read_request3 = addr;
658 break;
659 case(4):
660 assert(locked_read_request4 == Address(-1));
661 locked_read_request4 = addr;
662 break;
663 default:
664 assert(0);
665
666 }
738}
739
667}
668
740void ${ident}_Controller::started_writes()
669void ${ident}_Controller::clear_atomic(Address addr)
741{
670{
742 started_receiving_writes = true;
671
672 assert(servicing_atomic > 0);
673 if (addr == locked_read_request1)
674 locked_read_request1 = Address(-1);
675 else if (addr == locked_read_request2)
676 locked_read_request2 = Address(-1);
677 else if (addr == locked_read_request3)
678 locked_read_request3 = Address(-1);
679 else if (addr == locked_read_request4)
680 locked_read_request4 = Address(-1);
681 else
682 assert(0);
683 servicing_atomic--;
684
743}
744
685}
686
745void ${ident}_Controller::clear_atomic()
687void ${ident}_Controller::reset_atomics()
746{
688{
747 assert(servicing_atomic > 0);
748 read_counter--;
749 servicing_atomic--;
750 if (read_counter == 0) {
751 servicing_atomic = 0;
752 started_receiving_writes = false;
753 locked_read_request1 = Address(-1);
754 locked_read_request2 = Address(-1);
755 locked_read_request3 = Address(-1);
756 locked_read_request4 = Address(-1);
757 }
689
690 servicing_atomic = 0;
691 locked_read_request1 = Address(-1);
692 locked_read_request2 = Address(-1);
693 locked_read_request3 = Address(-1);
694 locked_read_request4 = Address(-1);
695
758}
696}
697
759''')
760 else:
761 code('''
698''')
699 else:
700 code('''
762void ${ident}_Controller::started_writes()
701void ${ident}_Controller::reset_atomics()
763{
764 assert(0);
765}
766
767void ${ident}_Controller::set_atomic(Address addr)
768{
769 assert(0);
770}
771
702{
703 assert(0);
704}
705
706void ${ident}_Controller::set_atomic(Address addr)
707{
708 assert(0);
709}
710
772void ${ident}_Controller::clear_atomic()
711void ${ident}_Controller::clear_atomic(Address addr)
773{
774 assert(0);
775}
776''')
777
778
779 code.write(path, "%s_Wakeup.cc" % self.ident)
780

--- 445 unchanged lines hidden --- 		712{
713 assert(0);
714}
715''')
716
717
718 code.write(path, "%s_Wakeup.cc" % self.ident)
719

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