1# Copyright (c) 1999-2008 Mark D. Hill and David A. Wood 2# Copyright (c) 2009 The Hewlett-Packard Development Company 3# All rights reserved. 4# 5# Redistribution and use in source and binary forms, with or without 6# modification, are permitted provided that the following conditions are 7# met: redistributions of source code must retain the above copyright 8# notice, this list of conditions and the following disclaimer; --- 172 unchanged lines hidden (view full) --- 181 const int & getVersion() const; 182 const string toString() const; 183 const string getName() const; 184 const MachineType getMachineType() const; 185 void print(ostream& out) const; 186 void printConfig(ostream& out) const; 187 void wakeup(); 188 void set_atomic(Address addr); |
189 void clear_atomic(Address addr); 190 void reset_atomics(); |
191 void printStats(ostream& out) const { s_profiler.dumpStats(out); } 192 void clearStats() { s_profiler.clearStats(); } 193private: 194''') 195 196 code.indent() 197 # added by SS 198 for param in self.config_parameters: 199 code('int m_${{param.ident}};') 200 201 if self.ident == "L1Cache": 202 code(''' 203int servicing_atomic; |
204Address locked_read_request1; 205Address locked_read_request2; 206Address locked_read_request3; 207Address locked_read_request4; 208int read_counter; 209''') 210 211 code(''' --- 83 unchanged lines hidden (view full) --- 295$c_ident::$c_ident(const string &name) 296 : m_name(name) 297{ 298''') 299 code.indent() 300 if self.ident == "L1Cache": 301 code(''' 302servicing_atomic = 0; |
303locked_read_request1 = Address(-1); 304locked_read_request2 = Address(-1); 305locked_read_request3 = Address(-1); 306locked_read_request4 = Address(-1); 307read_counter = 0; 308''') 309 310 code('m_num_controllers++;') --- 282 unchanged lines hidden (view full) --- 593 594 assert mandatory_q is not None 595 596 # print out the mandatory queue here 597 port = mandatory_q 598 code('// ${ident}InPort $port') 599 output = port["c_code_in_port"] 600 |
601 code('$output') 602 603 for port in self.in_ports: 604 # don't print out mandatory queue twice 605 if port == mandatory_q: 606 continue 607 608 if ident == "L1Cache": |
609 if (str(port).find("forwardRequestNetwork_in") >= 0 or str(port).find("requestNetwork_in") >= 0 or str(port).find("requestIntraChipL1Network_in") >= 0): |
610 code(''' 611bool postpone = false; 612if ((((*m_L1Cache_forwardToCache_ptr)).isReady())) { 613 const RequestMsg* in_msg_ptr; 614 in_msg_ptr = dynamic_cast<const RequestMsg*>(((*m_L1Cache_forwardToCache_ptr)).peek()); |
615 if ((((servicing_atomic > 0) && (locked_read_request1 == ((*in_msg_ptr)).m_Address || locked_read_request2 == ((*in_msg_ptr)).m_Address || locked_read_request3 == ((*in_msg_ptr)).m_Address || locked_read_request1 == ((*in_msg_ptr)).m_Address)))) { 616 postpone = true; |
617 } 618} 619if (!postpone) { 620''') 621 code.indent() 622 code('// ${ident}InPort $port') 623 code('${{port["c_code_in_port"]}}') 624 code.dedent() 625 626 if ident == "L1Cache": |
627 if (str(port).find("forwardRequestNetwork_in") >= 0 or str(port).find("requestNetwork_in") >= 0 or str(port).find("requestIntraChipL1Network_in") >= 0): |
628 code.dedent() 629 code('}') 630 code.indent() 631 code('') 632 633 code.dedent() 634 code.dedent() 635 code(''' 636 break; // If we got this far, we have nothing left todo 637 } 638} 639''') 640 641 if self.ident == "L1Cache": 642 code(''' 643void ${ident}_Controller::set_atomic(Address addr) 644{ 645 servicing_atomic++; |
646 switch (servicing_atomic) { 647 case(1): 648 assert(locked_read_request1 == Address(-1)); 649 locked_read_request1 = addr; 650 break; 651 case(2): 652 assert(locked_read_request2 == Address(-1)); 653 locked_read_request2 = addr; 654 break; 655 case(3): 656 assert(locked_read_request3 == Address(-1)); 657 locked_read_request3 = addr; 658 break; 659 case(4): 660 assert(locked_read_request4 == Address(-1)); 661 locked_read_request4 = addr; 662 break; 663 default: 664 assert(0); 665 666 } |
667} 668 |
669void ${ident}_Controller::clear_atomic(Address addr) |
670{ |
671 672 assert(servicing_atomic > 0); 673 if (addr == locked_read_request1) 674 locked_read_request1 = Address(-1); 675 else if (addr == locked_read_request2) 676 locked_read_request2 = Address(-1); 677 else if (addr == locked_read_request3) 678 locked_read_request3 = Address(-1); 679 else if (addr == locked_read_request4) 680 locked_read_request4 = Address(-1); 681 else 682 assert(0); 683 servicing_atomic--; 684 |
685} 686 |
687void ${ident}_Controller::reset_atomics() |
688{ |
689 690 servicing_atomic = 0; 691 locked_read_request1 = Address(-1); 692 locked_read_request2 = Address(-1); 693 locked_read_request3 = Address(-1); 694 locked_read_request4 = Address(-1); 695 |
696} |
697 |
698''') 699 else: 700 code(''' |
701void ${ident}_Controller::reset_atomics() |
702{ 703 assert(0); 704} 705 706void ${ident}_Controller::set_atomic(Address addr) 707{ 708 assert(0); 709} 710 |
711void ${ident}_Controller::clear_atomic(Address addr) |
712{ 713 assert(0); 714} 715''') 716 717 718 code.write(path, "%s_Wakeup.cc" % self.ident) 719 --- 445 unchanged lines hidden --- |