1# Copyright (c) 1999-2008 Mark D. Hill and David A. Wood 2# Copyright (c) 2009 The Hewlett-Packard Development Company 3# All rights reserved. 4# 5# Redistribution and use in source and binary forms, with or without 6# modification, are permitted provided that the following conditions are 7# met: redistributions of source code must retain the above copyright 8# notice, this list of conditions and the following disclaimer; --- 42 unchanged lines hidden (view full) --- 51 def __init__(self, symtab, ident, location, pairs, config_parameters): 52 super(StateMachine, self).__init__(symtab, ident, location, pairs) 53 self.table = None 54 self.config_parameters = config_parameters 55 self.prefetchers = [] 56 57 for param in config_parameters: 58 if param.pointer: |
59 var = Var(symtab, param.ident, location, param.type_ast.type, 60 "(*m_%s_ptr)" % param.ident, {}, self) |
61 else: |
62 var = Var(symtab, param.ident, location, param.type_ast.type, 63 "m_%s" % param.ident, {}, self) 64 65 self.symtab.registerSym(param.ident, var) 66 |
67 if str(param.type_ast.type) == "Prefetcher": 68 self.prefetchers.append(var) 69 70 self.states = orderdict() 71 self.events = orderdict() 72 self.actions = orderdict() 73 self.request_types = orderdict() 74 self.transitions = [] --- 100 unchanged lines hidden (view full) --- 175 self.printControllerHH(path) 176 self.printControllerCC(path, includes) 177 self.printCSwitch(path) 178 self.printCWakeup(path, includes) 179 180 def printControllerPython(self, path): 181 code = self.symtab.codeFormatter() 182 ident = self.ident |
183 |
184 py_ident = "%s_Controller" % ident 185 c_ident = "%s_Controller" % self.ident |
186 |
187 code(''' 188from m5.params import * 189from m5.SimObject import SimObject 190from Controller import RubyController 191 192class $py_ident(RubyController): 193 type = '$py_ident' 194 cxx_header = 'mem/protocol/${c_ident}.hh' 195''') 196 code.indent() 197 for param in self.config_parameters: 198 dflt_str = '' |
199 200 if param.rvalue is not None: 201 dflt_str = str(param.rvalue.inline()) + ', ' 202 |
203 if python_class_map.has_key(param.type_ast.type.c_ident): 204 python_type = python_class_map[param.type_ast.type.c_ident] |
205 code('${{param.ident}} = Param.${{python_type}}(${dflt_str}"")') 206 |
207 else: 208 self.error("Unknown c++ to python class conversion for c++ " \ 209 "type: '%s'. Please update the python_class_map " \ 210 "in StateMachine.py", param.type_ast.type.c_ident) 211 code.dedent() 212 code.write(path, '%s.py' % py_ident) 213 214 --- 267 unchanged lines hidden (view full) --- 482 483 # 484 # After initializing the universal machine parameters, initialize the 485 # this machines config parameters. Also if these configuration params 486 # include a sequencer, connect the it to the controller. 487 # 488 for param in self.config_parameters: 489 if param.pointer: |
490 code('m_${{param.ident}}_ptr = p->${{param.ident}};') |
491 else: |
492 code('m_${{param.ident}} = p->${{param.ident}};') 493 if re.compile("sequencer").search(param.ident): 494 code('m_${{param.ident}}_ptr->setController(this);') |
495 496 for var in self.objects: 497 if var.ident.find("mandatoryQueue") >= 0: 498 code(''' 499m_${{var.ident}}_ptr = new ${{var.type.c_ident}}(); 500m_${{var.ident}}_ptr->setReceiver(this); 501''') 502 else: --- 178 unchanged lines hidden (view full) --- 681 682 mq_ident = "NULL" 683 for port in self.in_ports: 684 if port.code.find("mandatoryQueue_ptr") >= 0: 685 mq_ident = "m_mandatoryQueue_ptr" 686 687 seq_ident = "NULL" 688 for param in self.config_parameters: |
689 if param.ident == "sequencer": |
690 assert(param.pointer) |
691 seq_ident = "m_%s_ptr" % param.ident |
692 693 code(''' 694 695void 696$c_ident::regStats() 697{ 698 AbstractController::regStats(); 699 --- 823 unchanged lines hidden --- |