1# Copyright (c) 1999-2008 Mark D. Hill and David A. Wood
2# Copyright (c) 2009 The Hewlett-Packard Development Company
3# All rights reserved.
4#
5# Redistribution and use in source and binary forms, with or without
6# modification, are permitted provided that the following conditions are
7# met: redistributions of source code must retain the above copyright
8# notice, this list of conditions and the following disclaimer;

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51 def __init__(self, symtab, ident, location, pairs, config_parameters):
52 super(StateMachine, self).__init__(symtab, ident, location, pairs)
53 self.table = None
54 self.config_parameters = config_parameters
55 self.prefetchers = []
56
57 for param in config_parameters:
58 if param.pointer:
59 var = Var(symtab, param.name, location, param.type_ast.type,
60 "(*m_%s_ptr)" % param.name, {}, self)
61 else:
62 var = Var(symtab, param.name, location, param.type_ast.type,
63 "m_%s" % param.name, {}, self)
64 self.symtab.registerSym(param.name, var)
65 if str(param.type_ast.type) == "Prefetcher":
66 self.prefetchers.append(var)
67
68 self.states = orderdict()
69 self.events = orderdict()
70 self.actions = orderdict()
71 self.request_types = orderdict()
72 self.transitions = []

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173 self.printControllerHH(path)
174 self.printControllerCC(path, includes)
175 self.printCSwitch(path)
176 self.printCWakeup(path, includes)
177
178 def printControllerPython(self, path):
179 code = self.symtab.codeFormatter()
180 ident = self.ident
181 py_ident = "%s_Controller" % ident
182 c_ident = "%s_Controller" % self.ident
183 code('''
184from m5.params import *
185from m5.SimObject import SimObject
186from Controller import RubyController
187
188class $py_ident(RubyController):
189 type = '$py_ident'
190 cxx_header = 'mem/protocol/${c_ident}.hh'
191''')
192 code.indent()
193 for param in self.config_parameters:
194 dflt_str = ''
195 if param.default is not None:
196 dflt_str = str(param.default) + ', '
197 if python_class_map.has_key(param.type_ast.type.c_ident):
198 python_type = python_class_map[param.type_ast.type.c_ident]
199 code('${{param.name}} = Param.${{python_type}}(${dflt_str}"")')
200 else:
201 self.error("Unknown c++ to python class conversion for c++ " \
202 "type: '%s'. Please update the python_class_map " \
203 "in StateMachine.py", param.type_ast.type.c_ident)
204 code.dedent()
205 code.write(path, '%s.py' % py_ident)
206
207

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475
476 #
477 # After initializing the universal machine parameters, initialize the
478 # this machines config parameters. Also if these configuration params
479 # include a sequencer, connect the it to the controller.
480 #
481 for param in self.config_parameters:
482 if param.pointer:
483 code('m_${{param.name}}_ptr = p->${{param.name}};')
484 else:
485 code('m_${{param.name}} = p->${{param.name}};')
486 if re.compile("sequencer").search(param.name):
487 code('m_${{param.name}}_ptr->setController(this);')
488
489 for var in self.objects:
490 if var.ident.find("mandatoryQueue") >= 0:
491 code('''
492m_${{var.ident}}_ptr = new ${{var.type.c_ident}}();
493m_${{var.ident}}_ptr->setReceiver(this);
494''')
495 else:

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674
675 mq_ident = "NULL"
676 for port in self.in_ports:
677 if port.code.find("mandatoryQueue_ptr") >= 0:
678 mq_ident = "m_mandatoryQueue_ptr"
679
680 seq_ident = "NULL"
681 for param in self.config_parameters:
682 if param.name == "sequencer":
683 assert(param.pointer)
684 seq_ident = "m_%s_ptr" % param.name
685
686 code('''
687
688void
689$c_ident::regStats()
690{
691 AbstractController::regStats();
692

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