1# Copyright (c) 1999-2008 Mark D. Hill and David A. Wood
2# Copyright (c) 2009 The Hewlett-Packard Development Company
3# All rights reserved.
4#
5# Redistribution and use in source and binary forms, with or without
6# modification, are permitted provided that the following conditions are
7# met: redistributions of source code must retain the above copyright
8# notice, this list of conditions and the following disclaimer;

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455#endif
456
457/** \\brief constructor */
458$c_ident::$c_ident(const Params *p)
459 : AbstractController(p)
460{
461 m_name = "${ident}";
462''')
463 num_in_ports = len(self.in_ports)
464 code(' m_in_ports = $num_in_ports;')
465 code.indent()
466
467 #
468 # After initializing the universal machine parameters, initialize the
469 # this machines config parameters. Also detemine if these configuration
470 # params include a sequencer. This information will be used later for
471 # contecting the sequencer back to the L1 cache controller.
472 #

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1095 code.indent()
1096
1097 # InPorts
1098 #
1099 for port in self.in_ports:
1100 code.indent()
1101 code('// ${ident}InPort $port')
1102 if port.pairs.has_key("rank"):
1103 code('m_cur_in_port = ${{port.pairs["rank"]}};')
1104 else:
1105 code('m_cur_in_port = 0;')
1106 code('${{port["c_code_in_port"]}}')
1107 code.dedent()
1108
1109 code('')
1110
1111 code.dedent()
1112 code.dedent()
1113 code('''

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