simple_mem.hh (9120:48eeef8a0997) simple_mem.hh (9228:bbdca4088834)
1/*
2 * Copyright (c) 2012 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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50#define __SIMPLE_MEMORY_HH__
51
52#include "mem/abstract_mem.hh"
53#include "mem/tport.hh"
54#include "params/SimpleMemory.hh"
55
56/**
57 * The simple memory is a basic single-ported memory controller with
1/*
2 * Copyright (c) 2012 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

--- 41 unchanged lines hidden (view full) ---

50#define __SIMPLE_MEMORY_HH__
51
52#include "mem/abstract_mem.hh"
53#include "mem/tport.hh"
54#include "params/SimpleMemory.hh"
55
56/**
57 * The simple memory is a basic single-ported memory controller with
58 * an infinite throughput and a fixed latency, potentially with a
59 * variance added to it. It uses a SimpleTimingPort to implement the
60 * timing accesses.
58 * an configurable throughput and latency, potentially with a variance
59 * added to the latter. It uses a QueueSlavePort to avoid dealing with
60 * the flow control of sending responses.
61 */
62class SimpleMemory : public AbstractMemory
63{
64
65 private:
66
61 */
62class SimpleMemory : public AbstractMemory
63{
64
65 private:
66
67 class MemoryPort : public SimpleTimingPort
67 class MemoryPort : public QueuedSlavePort
68 {
68 {
69
70 private:
71
72 /// Queue holding the response packets
73 SlavePacketQueue queueImpl;
69 SimpleMemory& memory;
70
71 public:
72
73 MemoryPort(const std::string& _name, SimpleMemory& _memory);
74
75 protected:
76
74 SimpleMemory& memory;
75
76 public:
77
78 MemoryPort(const std::string& _name, SimpleMemory& _memory);
79
80 protected:
81
77 virtual Tick recvAtomic(PacketPtr pkt);
82 Tick recvAtomic(PacketPtr pkt);
78
83
79 virtual void recvFunctional(PacketPtr pkt);
84 void recvFunctional(PacketPtr pkt);
80
85
81 virtual AddrRangeList getAddrRanges() const;
86 bool recvTimingReq(PacketPtr pkt);
82
87
88 AddrRangeList getAddrRanges() const;
89
83 };
84
85 MemoryPort port;
86
87 Tick lat;
88 Tick lat_var;
89
90 };
91
92 MemoryPort port;
93
94 Tick lat;
95 Tick lat_var;
96
97 /// Bandwidth in ticks per byte
98 const double bandwidth;
99
100 /**
101 * Track the state of the memory as either idle or busy, no need
102 * for an enum with only two states.
103 */
104 bool isBusy;
105
106 /**
107 * Remember if we have to retry an outstanding request that
108 * arrived while we were busy.
109 */
110 bool retryReq;
111
112 /**
113 * Release the memory after being busy and send a retry if a
114 * request was rejected in the meanwhile.
115 */
116 void release();
117
118 EventWrapper<SimpleMemory, &SimpleMemory::release> releaseEvent;
119
90 public:
91
120 public:
121
92 typedef SimpleMemoryParams Params;
93 SimpleMemory(const Params *p);
122 SimpleMemory(const SimpleMemoryParams *p);
94 virtual ~SimpleMemory() { }
95
96 unsigned int drain(Event* de);
97
98 virtual SlavePort& getSlavePort(const std::string& if_name, int idx = -1);
99 virtual void init();
100
123 virtual ~SimpleMemory() { }
124
125 unsigned int drain(Event* de);
126
127 virtual SlavePort& getSlavePort(const std::string& if_name, int idx = -1);
128 virtual void init();
129
101 const Params *
102 params() const
103 {
104 return dynamic_cast<const Params *>(_params);
105 }
106
107 protected:
108
109 Tick doAtomicAccess(PacketPtr pkt);
110 void doFunctionalAccess(PacketPtr pkt);
130 protected:
131
132 Tick doAtomicAccess(PacketPtr pkt);
133 void doFunctionalAccess(PacketPtr pkt);
111 virtual Tick calculateLatency(PacketPtr pkt);
134 bool recvTimingReq(PacketPtr pkt);
135 Tick calculateLatency(PacketPtr pkt);
112
113};
114
115#endif //__SIMPLE_MEMORY_HH__
136
137};
138
139#endif //__SIMPLE_MEMORY_HH__