simple_mem.hh (11190:0964165d1857) simple_mem.hh (11193:564e2e7e86f4)
1/*
2 * Copyright (c) 2012-2013 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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44/**
45 * @file
46 * SimpleMemory declaration
47 */
48
49#ifndef __SIMPLE_MEMORY_HH__
50#define __SIMPLE_MEMORY_HH__
51
1/*
2 * Copyright (c) 2012-2013 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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44/**
45 * @file
46 * SimpleMemory declaration
47 */
48
49#ifndef __SIMPLE_MEMORY_HH__
50#define __SIMPLE_MEMORY_HH__
51
52#include <deque>
52#include <list>
53
54#include "mem/abstract_mem.hh"
55#include "mem/port.hh"
56#include "params/SimpleMemory.hh"
57
58/**
59 * The simple memory is a basic single-ported memory controller with
60 * a configurable throughput and latency.

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120 */
121 const Tick latency_var;
122
123 /**
124 * Internal (unbounded) storage to mimic the delay caused by the
125 * actual memory access. Note that this is where the packet spends
126 * the memory latency.
127 */
53
54#include "mem/abstract_mem.hh"
55#include "mem/port.hh"
56#include "params/SimpleMemory.hh"
57
58/**
59 * The simple memory is a basic single-ported memory controller with
60 * a configurable throughput and latency.

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120 */
121 const Tick latency_var;
122
123 /**
124 * Internal (unbounded) storage to mimic the delay caused by the
125 * actual memory access. Note that this is where the packet spends
126 * the memory latency.
127 */
128 std::deque<DeferredPacket> packetQueue;
128 std::list<DeferredPacket> packetQueue;
129
130 /**
131 * Bandwidth in ticks per byte. The regulation affects the
132 * acceptance rate of requests and the queueing takes place after
133 * the regulation.
134 */
135 const double bandwidth;
136

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130 /**
131 * Bandwidth in ticks per byte. The regulation affects the
132 * acceptance rate of requests and the queueing takes place after
133 * the regulation.
134 */
135 const double bandwidth;
136

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