simple_mem.hh (11169:44b5c183c3cd) | simple_mem.hh (11190:0964165d1857) |
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1/* 2 * Copyright (c) 2012-2013 ARM Limited 3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software --- 161 unchanged lines hidden (view full) --- 170 171 /** 172 * Detemine the latency. 173 * 174 * @return the latency seen by the current packet 175 */ 176 Tick getLatency() const; 177 | 1/* 2 * Copyright (c) 2012-2013 ARM Limited 3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software --- 161 unchanged lines hidden (view full) --- 170 171 /** 172 * Detemine the latency. 173 * 174 * @return the latency seen by the current packet 175 */ 176 Tick getLatency() const; 177 |
178 /** @todo this is a temporary workaround until the 4-phase code is 179 * committed. upstream caches needs this packet until true is returned, so 180 * hold onto it for deletion until a subsequent call | 178 /** 179 * Upstream caches need this packet until true is returned, so 180 * hold it for deletion until a subsequent call |
181 */ | 181 */ |
182 std::vector<PacketPtr> pendingDelete; | 182 std::unique_ptr<Packet> pendingDelete; |
183 184 public: 185 186 SimpleMemory(const SimpleMemoryParams *p); 187 188 DrainState drain() override; 189 190 BaseSlavePort& getSlavePort(const std::string& if_name, --- 16 unchanged lines hidden --- | 183 184 public: 185 186 SimpleMemory(const SimpleMemoryParams *p); 187 188 DrainState drain() override; 189 190 BaseSlavePort& getSlavePort(const std::string& if_name, --- 16 unchanged lines hidden --- |