1/* 2 * Copyright (c) 2012 ARM Limited 3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software --- 40 unchanged lines hidden (view full) --- 49#ifndef __SIMPLE_MEMORY_HH__ 50#define __SIMPLE_MEMORY_HH__ 51 52#include "mem/abstract_mem.hh" 53#include "mem/tport.hh" 54#include "params/SimpleMemory.hh" 55 56/** |
57 * The simple memory is a basic single-ported memory controller with 58 * an infinite throughput and a fixed latency, potentially with a 59 * variance added to it. It uses a SimpleTimingPort to implement the 60 * timing accesses. |
61 */ 62class SimpleMemory : public AbstractMemory 63{ 64 65 private: 66 67 class MemoryPort : public SimpleTimingPort 68 { --- 8 unchanged lines hidden (view full) --- 77 virtual Tick recvAtomic(PacketPtr pkt); 78 79 virtual void recvFunctional(PacketPtr pkt); 80 81 virtual AddrRangeList getAddrRanges() const; 82 83 }; 84 |
85 MemoryPort port; |
86 87 Tick lat; 88 Tick lat_var; 89 90 public: 91 92 typedef SimpleMemoryParams Params; 93 SimpleMemory(const Params *p); --- 22 unchanged lines hidden --- |