2c2
< * Copyright (c) 2012 ARM Limited
---
> * Copyright (c) 2012-2013 ARM Limited
51a52,53
> #include <deque>
>
53c55
< #include "mem/tport.hh"
---
> #include "mem/port.hh"
58,60c60,61
< * an configurable throughput and latency, potentially with a variance
< * added to the latter. It uses a QueueSlavePort to avoid dealing with
< * the flow control of sending responses.
---
> * a configurable throughput and latency.
> *
68c69,73
< class MemoryPort : public QueuedSlavePort
---
> /**
> * A deferred packet stores a packet along with its scheduled
> * transmission time
> */
> class DeferredPacket
70a76,87
> public:
>
> const Tick tick;
> const PacketPtr pkt;
>
> DeferredPacket(PacketPtr _pkt, Tick _tick) : tick(_tick), pkt(_pkt)
> { }
> };
>
> class MemoryPort : public SlavePort
> {
>
73,74d89
< /// Queue holding the response packets
< SlavePacketQueue queueImpl;
88a104,105
> void recvRetry();
>
95,96c112,116
< Tick lat;
< Tick lat_var;
---
> /**
> * Latency from that a request is accepted until the response is
> * ready to be sent.
> */
> const Tick latency;
98c118,134
< /// Bandwidth in ticks per byte
---
> /**
> * Fudge factor added to the latency.
> */
> const Tick latency_var;
>
> /**
> * Internal (unbounded) storage to mimic the delay caused by the
> * actual memory access. Note that this is where the packet spends
> * the memory latency.
> */
> std::deque<DeferredPacket> packetQueue;
>
> /**
> * Bandwidth in ticks per byte. The regulation affects the
> * acceptance rate of requests and the queueing takes place after
> * the regulation.
> */
113a150,155
> * Remember if we failed to send a response and are awaiting a
> * retry. This is only used as a check.
> */
> bool retryResp;
>
> /**
120a163,177
> /**
> * Dequeue a packet from our internal packet queue and move it to
> * the port where it will be sent as soon as possible.
> */
> void dequeue();
>
> EventWrapper<SimpleMemory, &SimpleMemory::dequeue> dequeueEvent;
>
> /**
> * Detemine the latency.
> *
> * @return the latency seen by the current packet
> */
> Tick getLatency() const;
>
126a184,189
> /**
> * If we need to drain, keep the drain manager around until we're
> * done here.
> */
> DrainManager *drainManager;
>
130d192
< virtual ~SimpleMemory() { }
134,136c196,198
< virtual BaseSlavePort& getSlavePort(const std::string& if_name,
< PortID idx = InvalidPortID);
< virtual void init();
---
> BaseSlavePort& getSlavePort(const std::string& if_name,
> PortID idx = InvalidPortID);
> void init();
140,141c202,205
< Tick doAtomicAccess(PacketPtr pkt);
< void doFunctionalAccess(PacketPtr pkt);
---
> Tick recvAtomic(PacketPtr pkt);
>
> void recvFunctional(PacketPtr pkt);
>
143d206
< Tick calculateLatency(PacketPtr pkt);
144a208,209
> void recvRetry();
>