57,59c57,60
< * The simple memory is a basic multi-ported memory with an infinite
< * throughput and a fixed latency, potentially with a variance added
< * to it. It uses a SimpleTimingPort to implement the timing accesses.
---
> * The simple memory is a basic single-ported memory controller with
> * an infinite throughput and a fixed latency, potentially with a
> * variance added to it. It uses a SimpleTimingPort to implement the
> * timing accesses.
84c85
< std::vector<MemoryPort*> ports;
---
> MemoryPort port;