1/*
| 1/*
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2 * Copyright (c) 2012 ARM Limited
| 2 * Copyright (c) 2012-2013 ARM Limited
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3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software 9 * licensed hereunder. You may use the software subject to the license 10 * terms below provided that you ensure that this notice is replicated 11 * unmodified and in its entirety in all distributions of the software, 12 * modified or unmodified, in source code or in binary form. 13 * 14 * Copyright (c) 2001-2005 The Regents of The University of Michigan 15 * All rights reserved. 16 * 17 * Redistribution and use in source and binary forms, with or without 18 * modification, are permitted provided that the following conditions are 19 * met: redistributions of source code must retain the above copyright 20 * notice, this list of conditions and the following disclaimer; 21 * redistributions in binary form must reproduce the above copyright 22 * notice, this list of conditions and the following disclaimer in the 23 * documentation and/or other materials provided with the distribution; 24 * neither the name of the copyright holders nor the names of its 25 * contributors may be used to endorse or promote products derived from 26 * this software without specific prior written permission. 27 * 28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 39 * 40 * Authors: Ron Dreslinski 41 * Andreas Hansson 42 */ 43 44/** 45 * @file 46 * SimpleMemory declaration 47 */ 48 49#ifndef __SIMPLE_MEMORY_HH__ 50#define __SIMPLE_MEMORY_HH__ 51
| 3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software 9 * licensed hereunder. You may use the software subject to the license 10 * terms below provided that you ensure that this notice is replicated 11 * unmodified and in its entirety in all distributions of the software, 12 * modified or unmodified, in source code or in binary form. 13 * 14 * Copyright (c) 2001-2005 The Regents of The University of Michigan 15 * All rights reserved. 16 * 17 * Redistribution and use in source and binary forms, with or without 18 * modification, are permitted provided that the following conditions are 19 * met: redistributions of source code must retain the above copyright 20 * notice, this list of conditions and the following disclaimer; 21 * redistributions in binary form must reproduce the above copyright 22 * notice, this list of conditions and the following disclaimer in the 23 * documentation and/or other materials provided with the distribution; 24 * neither the name of the copyright holders nor the names of its 25 * contributors may be used to endorse or promote products derived from 26 * this software without specific prior written permission. 27 * 28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 39 * 40 * Authors: Ron Dreslinski 41 * Andreas Hansson 42 */ 43 44/** 45 * @file 46 * SimpleMemory declaration 47 */ 48 49#ifndef __SIMPLE_MEMORY_HH__ 50#define __SIMPLE_MEMORY_HH__ 51
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| 52#include <deque> 53
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52#include "mem/abstract_mem.hh"
| 54#include "mem/abstract_mem.hh"
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53#include "mem/tport.hh"
| 55#include "mem/port.hh"
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54#include "params/SimpleMemory.hh" 55 56/** 57 * The simple memory is a basic single-ported memory controller with
| 56#include "params/SimpleMemory.hh" 57 58/** 59 * The simple memory is a basic single-ported memory controller with
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58 * an configurable throughput and latency, potentially with a variance 59 * added to the latter. It uses a QueueSlavePort to avoid dealing with 60 * the flow control of sending responses.
| 60 * a configurable throughput and latency. 61 *
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61 * @sa \ref gem5MemorySystem "gem5 Memory System" 62 */ 63class SimpleMemory : public AbstractMemory 64{ 65 66 private: 67
| 62 * @sa \ref gem5MemorySystem "gem5 Memory System" 63 */ 64class SimpleMemory : public AbstractMemory 65{ 66 67 private: 68
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68 class MemoryPort : public QueuedSlavePort
| 69 /** 70 * A deferred packet stores a packet along with its scheduled 71 * transmission time 72 */ 73 class DeferredPacket
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69 { 70
| 74 { 75
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| 76 public: 77 78 const Tick tick; 79 const PacketPtr pkt; 80 81 DeferredPacket(PacketPtr _pkt, Tick _tick) : tick(_tick), pkt(_pkt) 82 { } 83 }; 84 85 class MemoryPort : public SlavePort 86 { 87
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71 private: 72
| 88 private: 89
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73 /// Queue holding the response packets 74 SlavePacketQueue queueImpl;
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75 SimpleMemory& memory; 76 77 public: 78 79 MemoryPort(const std::string& _name, SimpleMemory& _memory); 80 81 protected: 82 83 Tick recvAtomic(PacketPtr pkt); 84 85 void recvFunctional(PacketPtr pkt); 86 87 bool recvTimingReq(PacketPtr pkt); 88
| 90 SimpleMemory& memory; 91 92 public: 93 94 MemoryPort(const std::string& _name, SimpleMemory& _memory); 95 96 protected: 97 98 Tick recvAtomic(PacketPtr pkt); 99 100 void recvFunctional(PacketPtr pkt); 101 102 bool recvTimingReq(PacketPtr pkt); 103
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| 104 void recvRetry(); 105
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89 AddrRangeList getAddrRanges() const; 90 91 }; 92 93 MemoryPort port; 94
| 106 AddrRangeList getAddrRanges() const; 107 108 }; 109 110 MemoryPort port; 111
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95 Tick lat; 96 Tick lat_var;
| 112 /** 113 * Latency from that a request is accepted until the response is 114 * ready to be sent. 115 */ 116 const Tick latency;
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97
| 117
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98 /// Bandwidth in ticks per byte
| 118 /** 119 * Fudge factor added to the latency. 120 */ 121 const Tick latency_var; 122 123 /** 124 * Internal (unbounded) storage to mimic the delay caused by the 125 * actual memory access. Note that this is where the packet spends 126 * the memory latency. 127 */ 128 std::deque<DeferredPacket> packetQueue; 129 130 /** 131 * Bandwidth in ticks per byte. The regulation affects the 132 * acceptance rate of requests and the queueing takes place after 133 * the regulation. 134 */
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99 const double bandwidth; 100 101 /** 102 * Track the state of the memory as either idle or busy, no need 103 * for an enum with only two states. 104 */ 105 bool isBusy; 106 107 /** 108 * Remember if we have to retry an outstanding request that 109 * arrived while we were busy. 110 */ 111 bool retryReq; 112 113 /**
| 135 const double bandwidth; 136 137 /** 138 * Track the state of the memory as either idle or busy, no need 139 * for an enum with only two states. 140 */ 141 bool isBusy; 142 143 /** 144 * Remember if we have to retry an outstanding request that 145 * arrived while we were busy. 146 */ 147 bool retryReq; 148 149 /**
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| 150 * Remember if we failed to send a response and are awaiting a 151 * retry. This is only used as a check. 152 */ 153 bool retryResp; 154 155 /**
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114 * Release the memory after being busy and send a retry if a 115 * request was rejected in the meanwhile. 116 */ 117 void release(); 118 119 EventWrapper<SimpleMemory, &SimpleMemory::release> releaseEvent; 120
| 156 * Release the memory after being busy and send a retry if a 157 * request was rejected in the meanwhile. 158 */ 159 void release(); 160 161 EventWrapper<SimpleMemory, &SimpleMemory::release> releaseEvent; 162
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| 163 /** 164 * Dequeue a packet from our internal packet queue and move it to 165 * the port where it will be sent as soon as possible. 166 */ 167 void dequeue(); 168 169 EventWrapper<SimpleMemory, &SimpleMemory::dequeue> dequeueEvent; 170 171 /** 172 * Detemine the latency. 173 * 174 * @return the latency seen by the current packet 175 */ 176 Tick getLatency() const; 177
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121 /** @todo this is a temporary workaround until the 4-phase code is 122 * committed. upstream caches needs this packet until true is returned, so 123 * hold onto it for deletion until a subsequent call 124 */ 125 std::vector<PacketPtr> pendingDelete; 126
| 178 /** @todo this is a temporary workaround until the 4-phase code is 179 * committed. upstream caches needs this packet until true is returned, so 180 * hold onto it for deletion until a subsequent call 181 */ 182 std::vector<PacketPtr> pendingDelete; 183
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| 184 /** 185 * If we need to drain, keep the drain manager around until we're 186 * done here. 187 */ 188 DrainManager *drainManager; 189
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127 public: 128 129 SimpleMemory(const SimpleMemoryParams *p);
| 190 public: 191 192 SimpleMemory(const SimpleMemoryParams *p);
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130 virtual ~SimpleMemory() { }
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131 132 unsigned int drain(DrainManager *dm); 133
| 193 194 unsigned int drain(DrainManager *dm); 195
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134 virtual BaseSlavePort& getSlavePort(const std::string& if_name, 135 PortID idx = InvalidPortID); 136 virtual void init();
| 196 BaseSlavePort& getSlavePort(const std::string& if_name, 197 PortID idx = InvalidPortID); 198 void init();
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137 138 protected: 139
| 199 200 protected: 201
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140 Tick doAtomicAccess(PacketPtr pkt); 141 void doFunctionalAccess(PacketPtr pkt);
| 202 Tick recvAtomic(PacketPtr pkt); 203 204 void recvFunctional(PacketPtr pkt); 205
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142 bool recvTimingReq(PacketPtr pkt);
| 206 bool recvTimingReq(PacketPtr pkt);
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143 Tick calculateLatency(PacketPtr pkt);
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144
| 207
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| 208 void recvRetry(); 209
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145}; 146 147#endif //__SIMPLE_MEMORY_HH__
| 210}; 211 212#endif //__SIMPLE_MEMORY_HH__
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