1/*
2 * Copyright (c) 2012 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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49#ifndef __SIMPLE_MEMORY_HH__
50#define __SIMPLE_MEMORY_HH__
51
52#include "mem/abstract_mem.hh"
53#include "mem/tport.hh"
54#include "params/SimpleMemory.hh"
55
56/**
57 * The simple memory is a basic multi-ported memory with an infinite
58 * throughput and a fixed latency, potentially with a variance added
59 * to it. It uses a SimpleTimingPort to implement the timing accesses.
60 */
61class SimpleMemory : public AbstractMemory
62{
63
64 private:
65
66 class MemoryPort : public SimpleTimingPort
67 {

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76 virtual Tick recvAtomic(PacketPtr pkt);
77
78 virtual void recvFunctional(PacketPtr pkt);
79
80 virtual AddrRangeList getAddrRanges() const;
81
82 };
83
84 std::vector<MemoryPort*> ports;
85
86 Tick lat;
87 Tick lat_var;
88
89 public:
90
91 typedef SimpleMemoryParams Params;
92 SimpleMemory(const Params *p);

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