1/*
2 * Copyright (c) 2012-2013 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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176 Tick getLatency() const;
177
178 /** @todo this is a temporary workaround until the 4-phase code is
179 * committed. upstream caches needs this packet until true is returned, so
180 * hold onto it for deletion until a subsequent call
181 */
182 std::vector<PacketPtr> pendingDelete;
183
184 /**
185 * If we need to drain, keep the drain manager around until we're
186 * done here.
187 */
188 DrainManager *drainManager;
189
190 public:
191
192 SimpleMemory(const SimpleMemoryParams *p);
193
194 unsigned int drain(DrainManager *dm);
195
196 BaseSlavePort& getSlavePort(const std::string& if_name,
197 PortID idx = InvalidPortID);
198 void init();
199
200 protected:
201
202 Tick recvAtomic(PacketPtr pkt);
203
204 void recvFunctional(PacketPtr pkt);
205
206 bool recvTimingReq(PacketPtr pkt);
207
208 void recvRespRetry();
209
210};
211
212#endif //__SIMPLE_MEMORY_HH__