simple_mem.cc (11192:4c28abcf8249) simple_mem.cc (11193:564e2e7e86f4)
1/*
1/*
2 * Copyright (c) 2010-2013 ARM Limited
2 * Copyright (c) 2010-2013, 2015 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated

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111
112 // if we are busy with a read or write, remember that we have to
113 // retry
114 if (isBusy) {
115 retryReq = true;
116 return false;
117 }
118
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated

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111
112 // if we are busy with a read or write, remember that we have to
113 // retry
114 if (isBusy) {
115 retryReq = true;
116 return false;
117 }
118
119 // @todo someone should pay for this
119 // technically the packet only reaches us after the header delay,
120 // and since this is a memory controller we also need to
121 // deserialise the payload before performing any write operation
122 Tick receive_delay = pkt->headerDelay + pkt->payloadDelay;
120 pkt->headerDelay = pkt->payloadDelay = 0;
121
122 // update the release time according to the bandwidth limit, and
123 // do so with respect to the time it takes to finish this request
124 // rather than long term as it is the short term data rate that is
125 // limited for any real memory
126
127 // only look at reads and writes when determining if we are busy,

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145 // queue if there is one
146 bool needsResponse = pkt->needsResponse();
147 recvAtomic(pkt);
148 // turn packet around to go back to requester if response expected
149 if (needsResponse) {
150 // recvAtomic() should already have turned packet into
151 // atomic response
152 assert(pkt->isResponse());
123 pkt->headerDelay = pkt->payloadDelay = 0;
124
125 // update the release time according to the bandwidth limit, and
126 // do so with respect to the time it takes to finish this request
127 // rather than long term as it is the short term data rate that is
128 // limited for any real memory
129
130 // only look at reads and writes when determining if we are busy,

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148 // queue if there is one
149 bool needsResponse = pkt->needsResponse();
150 recvAtomic(pkt);
151 // turn packet around to go back to requester if response expected
152 if (needsResponse) {
153 // recvAtomic() should already have turned packet into
154 // atomic response
155 assert(pkt->isResponse());
153 // to keep things simple (and in order), we put the packet at
154 // the end even if the latency suggests it should be sent
155 // before the packet(s) before it
156 packetQueue.emplace_back(pkt, curTick() + getLatency());
156
157 Tick when_to_send = curTick() + receive_delay + getLatency();
158
159 // typically this should be added at the end, so start the
160 // insertion sort with the last element, also make sure not to
161 // re-order in front of some existing packet with the same
162 // address, the latter is important as this memory effectively
163 // hands out exclusive copies (shared is not asserted)
164 auto i = packetQueue.end();
165 --i;
166 while (i != packetQueue.begin() && when_to_send < i->tick &&
167 i->pkt->getAddr() != pkt->getAddr())
168 --i;
169
170 // emplace inserts the element before the position pointed to by
171 // the iterator, so advance it one step
172 packetQueue.emplace(++i, pkt, when_to_send);
173
157 if (!retryResp && !dequeueEvent.scheduled())
158 schedule(dequeueEvent, packetQueue.back().tick);
159 } else {
160 pendingDelete.reset(pkt);
161 }
162
163 return true;
164}

--- 115 unchanged lines hidden --- 		174 if (!retryResp && !dequeueEvent.scheduled())
175 schedule(dequeueEvent, packetQueue.back().tick);
176 } else {
177 pendingDelete.reset(pkt);
178 }
179
180 return true;
181}

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