1/*
2 * Copyright (c) 2010-2013, 2015 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2001-2005 The Regents of The University of Michigan
15 * All rights reserved.
16 *
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions are
19 * met: redistributions of source code must retain the above copyright
20 * notice, this list of conditions and the following disclaimer;
21 * redistributions in binary form must reproduce the above copyright
22 * notice, this list of conditions and the following disclaimer in the
23 * documentation and/or other materials provided with the distribution;
24 * neither the name of the copyright holders nor the names of its
25 * contributors may be used to endorse or promote products derived from
26 * this software without specific prior written permission.
27 *
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 *
40 * Authors: Ron Dreslinski
41 * Ali Saidi
42 * Andreas Hansson
43 */
44
45#include "mem/simple_mem.hh"
46
47#include "base/random.hh"
48#include "base/trace.hh"
49#include "debug/Drain.hh"
50
51SimpleMemory::SimpleMemory(const SimpleMemoryParams* p) :
52 AbstractMemory(p),
53 port(name() + ".port", *this), latency(p->latency),
54 latency_var(p->latency_var), bandwidth(p->bandwidth), isBusy(false),
55 retryReq(false), retryResp(false),
56 releaseEvent([this]{ release(); }, name()),
57 dequeueEvent([this]{ dequeue(); }, name())
58{
59}
60
61void
62SimpleMemory::init()
63{
64 AbstractMemory::init();
65
66 // allow unconnected memories as this is used in several ruby
67 // systems at the moment
68 if (port.isConnected()) {
69 port.sendRangeChange();
70 }
71}
72
73Tick
74SimpleMemory::recvAtomic(PacketPtr pkt)
75{
76 panic_if(pkt->cacheResponding(), "Should not see packets where cache "
77 "is responding");
78
79 access(pkt);
80 return getLatency();
81}
82
83Tick
84SimpleMemory::recvAtomicBackdoor(PacketPtr pkt, MemBackdoorPtr &_backdoor)
85{
86 Tick latency = recvAtomic(pkt);
87
88 if (backdoor.ptr())
89 _backdoor = &backdoor;
90 return latency;
91}
92
93void
94SimpleMemory::recvFunctional(PacketPtr pkt)
95{
96 pkt->pushLabel(name());
97
98 functionalAccess(pkt);
99
100 bool done = false;
101 auto p = packetQueue.begin();
102 // potentially update the packets in our packet queue as well
103 while (!done && p != packetQueue.end()) {
104 done = pkt->trySatisfyFunctional(p->pkt);
105 ++p;
106 }
107
108 pkt->popLabel();
109}
110
111bool
112SimpleMemory::recvTimingReq(PacketPtr pkt)
113{
114 panic_if(pkt->cacheResponding(), "Should not see packets where cache "
115 "is responding");
116
117 panic_if(!(pkt->isRead() || pkt->isWrite()),
118 "Should only see read and writes at memory controller, "
119 "saw %s to %#llx\n", pkt->cmdString(), pkt->getAddr());
120
121 // we should not get a new request after committing to retry the
122 // current one, but unfortunately the CPU violates this rule, so
123 // simply ignore it for now
124 if (retryReq)
125 return false;
126
127 // if we are busy with a read or write, remember that we have to
128 // retry
129 if (isBusy) {
130 retryReq = true;
131 return false;
132 }
133
134 // technically the packet only reaches us after the header delay,
135 // and since this is a memory controller we also need to
136 // deserialise the payload before performing any write operation
137 Tick receive_delay = pkt->headerDelay + pkt->payloadDelay;
138 pkt->headerDelay = pkt->payloadDelay = 0;
139
140 // update the release time according to the bandwidth limit, and
141 // do so with respect to the time it takes to finish this request
142 // rather than long term as it is the short term data rate that is
143 // limited for any real memory
144
145 // calculate an appropriate tick to release to not exceed
146 // the bandwidth limit
147 Tick duration = pkt->getSize() * bandwidth;
148
149 // only consider ourselves busy if there is any need to wait
150 // to avoid extra events being scheduled for (infinitely) fast
151 // memories
152 if (duration != 0) {
153 schedule(releaseEvent, curTick() + duration);
154 isBusy = true;
155 }
156
157 // go ahead and deal with the packet and put the response in the
158 // queue if there is one
159 bool needsResponse = pkt->needsResponse();
160 recvAtomic(pkt);
161 // turn packet around to go back to requester if response expected
162 if (needsResponse) {
163 // recvAtomic() should already have turned packet into
164 // atomic response
165 assert(pkt->isResponse());
166
167 Tick when_to_send = curTick() + receive_delay + getLatency();
168
169 // typically this should be added at the end, so start the
170 // insertion sort with the last element, also make sure not to
171 // re-order in front of some existing packet with the same
172 // address, the latter is important as this memory effectively
173 // hands out exclusive copies (shared is not asserted)
174 auto i = packetQueue.end();
175 --i;
176 while (i != packetQueue.begin() && when_to_send < i->tick &&
| 1/*
2 * Copyright (c) 2010-2013, 2015 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2001-2005 The Regents of The University of Michigan
15 * All rights reserved.
16 *
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions are
19 * met: redistributions of source code must retain the above copyright
20 * notice, this list of conditions and the following disclaimer;
21 * redistributions in binary form must reproduce the above copyright
22 * notice, this list of conditions and the following disclaimer in the
23 * documentation and/or other materials provided with the distribution;
24 * neither the name of the copyright holders nor the names of its
25 * contributors may be used to endorse or promote products derived from
26 * this software without specific prior written permission.
27 *
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 *
40 * Authors: Ron Dreslinski
41 * Ali Saidi
42 * Andreas Hansson
43 */
44
45#include "mem/simple_mem.hh"
46
47#include "base/random.hh"
48#include "base/trace.hh"
49#include "debug/Drain.hh"
50
51SimpleMemory::SimpleMemory(const SimpleMemoryParams* p) :
52 AbstractMemory(p),
53 port(name() + ".port", *this), latency(p->latency),
54 latency_var(p->latency_var), bandwidth(p->bandwidth), isBusy(false),
55 retryReq(false), retryResp(false),
56 releaseEvent([this]{ release(); }, name()),
57 dequeueEvent([this]{ dequeue(); }, name())
58{
59}
60
61void
62SimpleMemory::init()
63{
64 AbstractMemory::init();
65
66 // allow unconnected memories as this is used in several ruby
67 // systems at the moment
68 if (port.isConnected()) {
69 port.sendRangeChange();
70 }
71}
72
73Tick
74SimpleMemory::recvAtomic(PacketPtr pkt)
75{
76 panic_if(pkt->cacheResponding(), "Should not see packets where cache "
77 "is responding");
78
79 access(pkt);
80 return getLatency();
81}
82
83Tick
84SimpleMemory::recvAtomicBackdoor(PacketPtr pkt, MemBackdoorPtr &_backdoor)
85{
86 Tick latency = recvAtomic(pkt);
87
88 if (backdoor.ptr())
89 _backdoor = &backdoor;
90 return latency;
91}
92
93void
94SimpleMemory::recvFunctional(PacketPtr pkt)
95{
96 pkt->pushLabel(name());
97
98 functionalAccess(pkt);
99
100 bool done = false;
101 auto p = packetQueue.begin();
102 // potentially update the packets in our packet queue as well
103 while (!done && p != packetQueue.end()) {
104 done = pkt->trySatisfyFunctional(p->pkt);
105 ++p;
106 }
107
108 pkt->popLabel();
109}
110
111bool
112SimpleMemory::recvTimingReq(PacketPtr pkt)
113{
114 panic_if(pkt->cacheResponding(), "Should not see packets where cache "
115 "is responding");
116
117 panic_if(!(pkt->isRead() || pkt->isWrite()),
118 "Should only see read and writes at memory controller, "
119 "saw %s to %#llx\n", pkt->cmdString(), pkt->getAddr());
120
121 // we should not get a new request after committing to retry the
122 // current one, but unfortunately the CPU violates this rule, so
123 // simply ignore it for now
124 if (retryReq)
125 return false;
126
127 // if we are busy with a read or write, remember that we have to
128 // retry
129 if (isBusy) {
130 retryReq = true;
131 return false;
132 }
133
134 // technically the packet only reaches us after the header delay,
135 // and since this is a memory controller we also need to
136 // deserialise the payload before performing any write operation
137 Tick receive_delay = pkt->headerDelay + pkt->payloadDelay;
138 pkt->headerDelay = pkt->payloadDelay = 0;
139
140 // update the release time according to the bandwidth limit, and
141 // do so with respect to the time it takes to finish this request
142 // rather than long term as it is the short term data rate that is
143 // limited for any real memory
144
145 // calculate an appropriate tick to release to not exceed
146 // the bandwidth limit
147 Tick duration = pkt->getSize() * bandwidth;
148
149 // only consider ourselves busy if there is any need to wait
150 // to avoid extra events being scheduled for (infinitely) fast
151 // memories
152 if (duration != 0) {
153 schedule(releaseEvent, curTick() + duration);
154 isBusy = true;
155 }
156
157 // go ahead and deal with the packet and put the response in the
158 // queue if there is one
159 bool needsResponse = pkt->needsResponse();
160 recvAtomic(pkt);
161 // turn packet around to go back to requester if response expected
162 if (needsResponse) {
163 // recvAtomic() should already have turned packet into
164 // atomic response
165 assert(pkt->isResponse());
166
167 Tick when_to_send = curTick() + receive_delay + getLatency();
168
169 // typically this should be added at the end, so start the
170 // insertion sort with the last element, also make sure not to
171 // re-order in front of some existing packet with the same
172 // address, the latter is important as this memory effectively
173 // hands out exclusive copies (shared is not asserted)
174 auto i = packetQueue.end();
175 --i;
176 while (i != packetQueue.begin() && when_to_send < i->tick &&
|
178 --i;
179
180 // emplace inserts the element before the position pointed to by
181 // the iterator, so advance it one step
182 packetQueue.emplace(++i, pkt, when_to_send);
183
184 if (!retryResp && !dequeueEvent.scheduled())
185 schedule(dequeueEvent, packetQueue.back().tick);
186 } else {
187 pendingDelete.reset(pkt);
188 }
189
190 return true;
191}
192
193void
194SimpleMemory::release()
195{
196 assert(isBusy);
197 isBusy = false;
198 if (retryReq) {
199 retryReq = false;
200 port.sendRetryReq();
201 }
202}
203
204void
205SimpleMemory::dequeue()
206{
207 assert(!packetQueue.empty());
208 DeferredPacket deferred_pkt = packetQueue.front();
209
210 retryResp = !port.sendTimingResp(deferred_pkt.pkt);
211
212 if (!retryResp) {
213 packetQueue.pop_front();
214
215 // if the queue is not empty, schedule the next dequeue event,
216 // otherwise signal that we are drained if we were asked to do so
217 if (!packetQueue.empty()) {
218 // if there were packets that got in-between then we
219 // already have an event scheduled, so use re-schedule
220 reschedule(dequeueEvent,
221 std::max(packetQueue.front().tick, curTick()), true);
222 } else if (drainState() == DrainState::Draining) {
223 DPRINTF(Drain, "Draining of SimpleMemory complete\n");
224 signalDrainDone();
225 }
226 }
227}
228
229Tick
230SimpleMemory::getLatency() const
231{
232 return latency +
233 (latency_var ? random_mt.random<Tick>(0, latency_var) : 0);
234}
235
236void
237SimpleMemory::recvRespRetry()
238{
239 assert(retryResp);
240
241 dequeue();
242}
243
244Port &
245SimpleMemory::getPort(const std::string &if_name, PortID idx)
246{
247 if (if_name != "port") {
248 return MemObject::getPort(if_name, idx);
249 } else {
250 return port;
251 }
252}
253
254DrainState
255SimpleMemory::drain()
256{
257 if (!packetQueue.empty()) {
258 DPRINTF(Drain, "SimpleMemory Queue has requests, waiting to drain\n");
259 return DrainState::Draining;
260 } else {
261 return DrainState::Drained;
262 }
263}
264
265SimpleMemory::MemoryPort::MemoryPort(const std::string& _name,
266 SimpleMemory& _memory)
267 : SlavePort(_name, &_memory), memory(_memory)
268{ }
269
270AddrRangeList
271SimpleMemory::MemoryPort::getAddrRanges() const
272{
273 AddrRangeList ranges;
274 ranges.push_back(memory.getAddrRange());
275 return ranges;
276}
277
278Tick
279SimpleMemory::MemoryPort::recvAtomic(PacketPtr pkt)
280{
281 return memory.recvAtomic(pkt);
282}
283
284Tick
285SimpleMemory::MemoryPort::recvAtomicBackdoor(
286 PacketPtr pkt, MemBackdoorPtr &_backdoor)
287{
288 return memory.recvAtomicBackdoor(pkt, _backdoor);
289}
290
291void
292SimpleMemory::MemoryPort::recvFunctional(PacketPtr pkt)
293{
294 memory.recvFunctional(pkt);
295}
296
297bool
298SimpleMemory::MemoryPort::recvTimingReq(PacketPtr pkt)
299{
300 return memory.recvTimingReq(pkt);
301}
302
303void
304SimpleMemory::MemoryPort::recvRespRetry()
305{
306 memory.recvRespRetry();
307}
308
309SimpleMemory*
310SimpleMemoryParams::create()
311{
312 return new SimpleMemory(this);
313}
| 178 --i;
179
180 // emplace inserts the element before the position pointed to by
181 // the iterator, so advance it one step
182 packetQueue.emplace(++i, pkt, when_to_send);
183
184 if (!retryResp && !dequeueEvent.scheduled())
185 schedule(dequeueEvent, packetQueue.back().tick);
186 } else {
187 pendingDelete.reset(pkt);
188 }
189
190 return true;
191}
192
193void
194SimpleMemory::release()
195{
196 assert(isBusy);
197 isBusy = false;
198 if (retryReq) {
199 retryReq = false;
200 port.sendRetryReq();
201 }
202}
203
204void
205SimpleMemory::dequeue()
206{
207 assert(!packetQueue.empty());
208 DeferredPacket deferred_pkt = packetQueue.front();
209
210 retryResp = !port.sendTimingResp(deferred_pkt.pkt);
211
212 if (!retryResp) {
213 packetQueue.pop_front();
214
215 // if the queue is not empty, schedule the next dequeue event,
216 // otherwise signal that we are drained if we were asked to do so
217 if (!packetQueue.empty()) {
218 // if there were packets that got in-between then we
219 // already have an event scheduled, so use re-schedule
220 reschedule(dequeueEvent,
221 std::max(packetQueue.front().tick, curTick()), true);
222 } else if (drainState() == DrainState::Draining) {
223 DPRINTF(Drain, "Draining of SimpleMemory complete\n");
224 signalDrainDone();
225 }
226 }
227}
228
229Tick
230SimpleMemory::getLatency() const
231{
232 return latency +
233 (latency_var ? random_mt.random<Tick>(0, latency_var) : 0);
234}
235
236void
237SimpleMemory::recvRespRetry()
238{
239 assert(retryResp);
240
241 dequeue();
242}
243
244Port &
245SimpleMemory::getPort(const std::string &if_name, PortID idx)
246{
247 if (if_name != "port") {
248 return MemObject::getPort(if_name, idx);
249 } else {
250 return port;
251 }
252}
253
254DrainState
255SimpleMemory::drain()
256{
257 if (!packetQueue.empty()) {
258 DPRINTF(Drain, "SimpleMemory Queue has requests, waiting to drain\n");
259 return DrainState::Draining;
260 } else {
261 return DrainState::Drained;
262 }
263}
264
265SimpleMemory::MemoryPort::MemoryPort(const std::string& _name,
266 SimpleMemory& _memory)
267 : SlavePort(_name, &_memory), memory(_memory)
268{ }
269
270AddrRangeList
271SimpleMemory::MemoryPort::getAddrRanges() const
272{
273 AddrRangeList ranges;
274 ranges.push_back(memory.getAddrRange());
275 return ranges;
276}
277
278Tick
279SimpleMemory::MemoryPort::recvAtomic(PacketPtr pkt)
280{
281 return memory.recvAtomic(pkt);
282}
283
284Tick
285SimpleMemory::MemoryPort::recvAtomicBackdoor(
286 PacketPtr pkt, MemBackdoorPtr &_backdoor)
287{
288 return memory.recvAtomicBackdoor(pkt, _backdoor);
289}
290
291void
292SimpleMemory::MemoryPort::recvFunctional(PacketPtr pkt)
293{
294 memory.recvFunctional(pkt);
295}
296
297bool
298SimpleMemory::MemoryPort::recvTimingReq(PacketPtr pkt)
299{
300 return memory.recvTimingReq(pkt);
301}
302
303void
304SimpleMemory::MemoryPort::recvRespRetry()
305{
306 memory.recvRespRetry();
307}
308
309SimpleMemory*
310SimpleMemoryParams::create()
311{
312 return new SimpleMemory(this);
313}
|