simple_mem.cc (12084:5a3769ff3d55) simple_mem.cc (12637:bfc3cb9c7e6c)
1/*
2 * Copyright (c) 2010-2013, 2015 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2001-2005 The Regents of The University of Michigan
15 * All rights reserved.
16 *
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions are
19 * met: redistributions of source code must retain the above copyright
20 * notice, this list of conditions and the following disclaimer;
21 * redistributions in binary form must reproduce the above copyright
22 * notice, this list of conditions and the following disclaimer in the
23 * documentation and/or other materials provided with the distribution;
24 * neither the name of the copyright holders nor the names of its
25 * contributors may be used to endorse or promote products derived from
26 * this software without specific prior written permission.
27 *
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 *
40 * Authors: Ron Dreslinski
41 * Ali Saidi
42 * Andreas Hansson
43 */
44
45#include "mem/simple_mem.hh"
46
47#include "base/random.hh"
48#include "base/trace.hh"
49#include "debug/Drain.hh"
50
1/*
2 * Copyright (c) 2010-2013, 2015 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2001-2005 The Regents of The University of Michigan
15 * All rights reserved.
16 *
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions are
19 * met: redistributions of source code must retain the above copyright
20 * notice, this list of conditions and the following disclaimer;
21 * redistributions in binary form must reproduce the above copyright
22 * notice, this list of conditions and the following disclaimer in the
23 * documentation and/or other materials provided with the distribution;
24 * neither the name of the copyright holders nor the names of its
25 * contributors may be used to endorse or promote products derived from
26 * this software without specific prior written permission.
27 *
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 *
40 * Authors: Ron Dreslinski
41 * Ali Saidi
42 * Andreas Hansson
43 */
44
45#include "mem/simple_mem.hh"
46
47#include "base/random.hh"
48#include "base/trace.hh"
49#include "debug/Drain.hh"
50
51using namespace std;
52
53SimpleMemory::SimpleMemory(const SimpleMemoryParams* p) :
54 AbstractMemory(p),
55 port(name() + ".port", *this), latency(p->latency),
56 latency_var(p->latency_var), bandwidth(p->bandwidth), isBusy(false),
57 retryReq(false), retryResp(false),
58 releaseEvent([this]{ release(); }, name()),
59 dequeueEvent([this]{ dequeue(); }, name())
60{
61}
62
63void
64SimpleMemory::init()
65{
66 AbstractMemory::init();
67
68 // allow unconnected memories as this is used in several ruby
69 // systems at the moment
70 if (port.isConnected()) {
71 port.sendRangeChange();
72 }
73}
74
75Tick
76SimpleMemory::recvAtomic(PacketPtr pkt)
77{
78 panic_if(pkt->cacheResponding(), "Should not see packets where cache "
79 "is responding");
80
81 access(pkt);
82 return getLatency();
83}
84
85void
86SimpleMemory::recvFunctional(PacketPtr pkt)
87{
88 pkt->pushLabel(name());
89
90 functionalAccess(pkt);
91
92 bool done = false;
93 auto p = packetQueue.begin();
94 // potentially update the packets in our packet queue as well
95 while (!done && p != packetQueue.end()) {
96 done = pkt->checkFunctional(p->pkt);
97 ++p;
98 }
99
100 pkt->popLabel();
101}
102
103bool
104SimpleMemory::recvTimingReq(PacketPtr pkt)
105{
106 panic_if(pkt->cacheResponding(), "Should not see packets where cache "
107 "is responding");
108
109 panic_if(!(pkt->isRead() || pkt->isWrite()),
110 "Should only see read and writes at memory controller, "
111 "saw %s to %#llx\n", pkt->cmdString(), pkt->getAddr());
112
113 // we should not get a new request after committing to retry the
114 // current one, but unfortunately the CPU violates this rule, so
115 // simply ignore it for now
116 if (retryReq)
117 return false;
118
119 // if we are busy with a read or write, remember that we have to
120 // retry
121 if (isBusy) {
122 retryReq = true;
123 return false;
124 }
125
126 // technically the packet only reaches us after the header delay,
127 // and since this is a memory controller we also need to
128 // deserialise the payload before performing any write operation
129 Tick receive_delay = pkt->headerDelay + pkt->payloadDelay;
130 pkt->headerDelay = pkt->payloadDelay = 0;
131
132 // update the release time according to the bandwidth limit, and
133 // do so with respect to the time it takes to finish this request
134 // rather than long term as it is the short term data rate that is
135 // limited for any real memory
136
137 // calculate an appropriate tick to release to not exceed
138 // the bandwidth limit
139 Tick duration = pkt->getSize() * bandwidth;
140
141 // only consider ourselves busy if there is any need to wait
142 // to avoid extra events being scheduled for (infinitely) fast
143 // memories
144 if (duration != 0) {
145 schedule(releaseEvent, curTick() + duration);
146 isBusy = true;
147 }
148
149 // go ahead and deal with the packet and put the response in the
150 // queue if there is one
151 bool needsResponse = pkt->needsResponse();
152 recvAtomic(pkt);
153 // turn packet around to go back to requester if response expected
154 if (needsResponse) {
155 // recvAtomic() should already have turned packet into
156 // atomic response
157 assert(pkt->isResponse());
158
159 Tick when_to_send = curTick() + receive_delay + getLatency();
160
161 // typically this should be added at the end, so start the
162 // insertion sort with the last element, also make sure not to
163 // re-order in front of some existing packet with the same
164 // address, the latter is important as this memory effectively
165 // hands out exclusive copies (shared is not asserted)
166 auto i = packetQueue.end();
167 --i;
168 while (i != packetQueue.begin() && when_to_send < i->tick &&
169 i->pkt->getAddr() != pkt->getAddr())
170 --i;
171
172 // emplace inserts the element before the position pointed to by
173 // the iterator, so advance it one step
174 packetQueue.emplace(++i, pkt, when_to_send);
175
176 if (!retryResp && !dequeueEvent.scheduled())
177 schedule(dequeueEvent, packetQueue.back().tick);
178 } else {
179 pendingDelete.reset(pkt);
180 }
181
182 return true;
183}
184
185void
186SimpleMemory::release()
187{
188 assert(isBusy);
189 isBusy = false;
190 if (retryReq) {
191 retryReq = false;
192 port.sendRetryReq();
193 }
194}
195
196void
197SimpleMemory::dequeue()
198{
199 assert(!packetQueue.empty());
200 DeferredPacket deferred_pkt = packetQueue.front();
201
202 retryResp = !port.sendTimingResp(deferred_pkt.pkt);
203
204 if (!retryResp) {
205 packetQueue.pop_front();
206
207 // if the queue is not empty, schedule the next dequeue event,
208 // otherwise signal that we are drained if we were asked to do so
209 if (!packetQueue.empty()) {
210 // if there were packets that got in-between then we
211 // already have an event scheduled, so use re-schedule
212 reschedule(dequeueEvent,
213 std::max(packetQueue.front().tick, curTick()), true);
214 } else if (drainState() == DrainState::Draining) {
215 DPRINTF(Drain, "Draining of SimpleMemory complete\n");
216 signalDrainDone();
217 }
218 }
219}
220
221Tick
222SimpleMemory::getLatency() const
223{
224 return latency +
225 (latency_var ? random_mt.random<Tick>(0, latency_var) : 0);
226}
227
228void
229SimpleMemory::recvRespRetry()
230{
231 assert(retryResp);
232
233 dequeue();
234}
235
236BaseSlavePort &
237SimpleMemory::getSlavePort(const std::string &if_name, PortID idx)
238{
239 if (if_name != "port") {
240 return MemObject::getSlavePort(if_name, idx);
241 } else {
242 return port;
243 }
244}
245
246DrainState
247SimpleMemory::drain()
248{
249 if (!packetQueue.empty()) {
250 DPRINTF(Drain, "SimpleMemory Queue has requests, waiting to drain\n");
251 return DrainState::Draining;
252 } else {
253 return DrainState::Drained;
254 }
255}
256
257SimpleMemory::MemoryPort::MemoryPort(const std::string& _name,
258 SimpleMemory& _memory)
259 : SlavePort(_name, &_memory), memory(_memory)
260{ }
261
262AddrRangeList
263SimpleMemory::MemoryPort::getAddrRanges() const
264{
265 AddrRangeList ranges;
266 ranges.push_back(memory.getAddrRange());
267 return ranges;
268}
269
270Tick
271SimpleMemory::MemoryPort::recvAtomic(PacketPtr pkt)
272{
273 return memory.recvAtomic(pkt);
274}
275
276void
277SimpleMemory::MemoryPort::recvFunctional(PacketPtr pkt)
278{
279 memory.recvFunctional(pkt);
280}
281
282bool
283SimpleMemory::MemoryPort::recvTimingReq(PacketPtr pkt)
284{
285 return memory.recvTimingReq(pkt);
286}
287
288void
289SimpleMemory::MemoryPort::recvRespRetry()
290{
291 memory.recvRespRetry();
292}
293
294SimpleMemory*
295SimpleMemoryParams::create()
296{
297 return new SimpleMemory(this);
298}
51SimpleMemory::SimpleMemory(const SimpleMemoryParams* p) :
52 AbstractMemory(p),
53 port(name() + ".port", *this), latency(p->latency),
54 latency_var(p->latency_var), bandwidth(p->bandwidth), isBusy(false),
55 retryReq(false), retryResp(false),
56 releaseEvent([this]{ release(); }, name()),
57 dequeueEvent([this]{ dequeue(); }, name())
58{
59}
60
61void
62SimpleMemory::init()
63{
64 AbstractMemory::init();
65
66 // allow unconnected memories as this is used in several ruby
67 // systems at the moment
68 if (port.isConnected()) {
69 port.sendRangeChange();
70 }
71}
72
73Tick
74SimpleMemory::recvAtomic(PacketPtr pkt)
75{
76 panic_if(pkt->cacheResponding(), "Should not see packets where cache "
77 "is responding");
78
79 access(pkt);
80 return getLatency();
81}
82
83void
84SimpleMemory::recvFunctional(PacketPtr pkt)
85{
86 pkt->pushLabel(name());
87
88 functionalAccess(pkt);
89
90 bool done = false;
91 auto p = packetQueue.begin();
92 // potentially update the packets in our packet queue as well
93 while (!done && p != packetQueue.end()) {
94 done = pkt->checkFunctional(p->pkt);
95 ++p;
96 }
97
98 pkt->popLabel();
99}
100
101bool
102SimpleMemory::recvTimingReq(PacketPtr pkt)
103{
104 panic_if(pkt->cacheResponding(), "Should not see packets where cache "
105 "is responding");
106
107 panic_if(!(pkt->isRead() || pkt->isWrite()),
108 "Should only see read and writes at memory controller, "
109 "saw %s to %#llx\n", pkt->cmdString(), pkt->getAddr());
110
111 // we should not get a new request after committing to retry the
112 // current one, but unfortunately the CPU violates this rule, so
113 // simply ignore it for now
114 if (retryReq)
115 return false;
116
117 // if we are busy with a read or write, remember that we have to
118 // retry
119 if (isBusy) {
120 retryReq = true;
121 return false;
122 }
123
124 // technically the packet only reaches us after the header delay,
125 // and since this is a memory controller we also need to
126 // deserialise the payload before performing any write operation
127 Tick receive_delay = pkt->headerDelay + pkt->payloadDelay;
128 pkt->headerDelay = pkt->payloadDelay = 0;
129
130 // update the release time according to the bandwidth limit, and
131 // do so with respect to the time it takes to finish this request
132 // rather than long term as it is the short term data rate that is
133 // limited for any real memory
134
135 // calculate an appropriate tick to release to not exceed
136 // the bandwidth limit
137 Tick duration = pkt->getSize() * bandwidth;
138
139 // only consider ourselves busy if there is any need to wait
140 // to avoid extra events being scheduled for (infinitely) fast
141 // memories
142 if (duration != 0) {
143 schedule(releaseEvent, curTick() + duration);
144 isBusy = true;
145 }
146
147 // go ahead and deal with the packet and put the response in the
148 // queue if there is one
149 bool needsResponse = pkt->needsResponse();
150 recvAtomic(pkt);
151 // turn packet around to go back to requester if response expected
152 if (needsResponse) {
153 // recvAtomic() should already have turned packet into
154 // atomic response
155 assert(pkt->isResponse());
156
157 Tick when_to_send = curTick() + receive_delay + getLatency();
158
159 // typically this should be added at the end, so start the
160 // insertion sort with the last element, also make sure not to
161 // re-order in front of some existing packet with the same
162 // address, the latter is important as this memory effectively
163 // hands out exclusive copies (shared is not asserted)
164 auto i = packetQueue.end();
165 --i;
166 while (i != packetQueue.begin() && when_to_send < i->tick &&
167 i->pkt->getAddr() != pkt->getAddr())
168 --i;
169
170 // emplace inserts the element before the position pointed to by
171 // the iterator, so advance it one step
172 packetQueue.emplace(++i, pkt, when_to_send);
173
174 if (!retryResp && !dequeueEvent.scheduled())
175 schedule(dequeueEvent, packetQueue.back().tick);
176 } else {
177 pendingDelete.reset(pkt);
178 }
179
180 return true;
181}
182
183void
184SimpleMemory::release()
185{
186 assert(isBusy);
187 isBusy = false;
188 if (retryReq) {
189 retryReq = false;
190 port.sendRetryReq();
191 }
192}
193
194void
195SimpleMemory::dequeue()
196{
197 assert(!packetQueue.empty());
198 DeferredPacket deferred_pkt = packetQueue.front();
199
200 retryResp = !port.sendTimingResp(deferred_pkt.pkt);
201
202 if (!retryResp) {
203 packetQueue.pop_front();
204
205 // if the queue is not empty, schedule the next dequeue event,
206 // otherwise signal that we are drained if we were asked to do so
207 if (!packetQueue.empty()) {
208 // if there were packets that got in-between then we
209 // already have an event scheduled, so use re-schedule
210 reschedule(dequeueEvent,
211 std::max(packetQueue.front().tick, curTick()), true);
212 } else if (drainState() == DrainState::Draining) {
213 DPRINTF(Drain, "Draining of SimpleMemory complete\n");
214 signalDrainDone();
215 }
216 }
217}
218
219Tick
220SimpleMemory::getLatency() const
221{
222 return latency +
223 (latency_var ? random_mt.random<Tick>(0, latency_var) : 0);
224}
225
226void
227SimpleMemory::recvRespRetry()
228{
229 assert(retryResp);
230
231 dequeue();
232}
233
234BaseSlavePort &
235SimpleMemory::getSlavePort(const std::string &if_name, PortID idx)
236{
237 if (if_name != "port") {
238 return MemObject::getSlavePort(if_name, idx);
239 } else {
240 return port;
241 }
242}
243
244DrainState
245SimpleMemory::drain()
246{
247 if (!packetQueue.empty()) {
248 DPRINTF(Drain, "SimpleMemory Queue has requests, waiting to drain\n");
249 return DrainState::Draining;
250 } else {
251 return DrainState::Drained;
252 }
253}
254
255SimpleMemory::MemoryPort::MemoryPort(const std::string& _name,
256 SimpleMemory& _memory)
257 : SlavePort(_name, &_memory), memory(_memory)
258{ }
259
260AddrRangeList
261SimpleMemory::MemoryPort::getAddrRanges() const
262{
263 AddrRangeList ranges;
264 ranges.push_back(memory.getAddrRange());
265 return ranges;
266}
267
268Tick
269SimpleMemory::MemoryPort::recvAtomic(PacketPtr pkt)
270{
271 return memory.recvAtomic(pkt);
272}
273
274void
275SimpleMemory::MemoryPort::recvFunctional(PacketPtr pkt)
276{
277 memory.recvFunctional(pkt);
278}
279
280bool
281SimpleMemory::MemoryPort::recvTimingReq(PacketPtr pkt)
282{
283 return memory.recvTimingReq(pkt);
284}
285
286void
287SimpleMemory::MemoryPort::recvRespRetry()
288{
289 memory.recvRespRetry();
290}
291
292SimpleMemory*
293SimpleMemoryParams::create()
294{
295 return new SimpleMemory(this);
296}