1/*
2 * Copyright (c) 2010-2013, 2015 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2001-2005 The Regents of The University of Michigan
15 * All rights reserved.
16 *
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions are
19 * met: redistributions of source code must retain the above copyright
20 * notice, this list of conditions and the following disclaimer;
21 * redistributions in binary form must reproduce the above copyright
22 * notice, this list of conditions and the following disclaimer in the
23 * documentation and/or other materials provided with the distribution;
24 * neither the name of the copyright holders nor the names of its
25 * contributors may be used to endorse or promote products derived from
26 * this software without specific prior written permission.
27 *
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 *
40 * Authors: Ron Dreslinski
41 * Ali Saidi
42 * Andreas Hansson
43 */
44
| 1/*
2 * Copyright (c) 2010-2013, 2015 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2001-2005 The Regents of The University of Michigan
15 * All rights reserved.
16 *
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions are
19 * met: redistributions of source code must retain the above copyright
20 * notice, this list of conditions and the following disclaimer;
21 * redistributions in binary form must reproduce the above copyright
22 * notice, this list of conditions and the following disclaimer in the
23 * documentation and/or other materials provided with the distribution;
24 * neither the name of the copyright holders nor the names of its
25 * contributors may be used to endorse or promote products derived from
26 * this software without specific prior written permission.
27 *
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 *
40 * Authors: Ron Dreslinski
41 * Ali Saidi
42 * Andreas Hansson
43 */
44
|
47#include "debug/Drain.hh"
48
49using namespace std;
50
51SimpleMemory::SimpleMemory(const SimpleMemoryParams* p) :
52 AbstractMemory(p),
53 port(name() + ".port", *this), latency(p->latency),
54 latency_var(p->latency_var), bandwidth(p->bandwidth), isBusy(false),
55 retryReq(false), retryResp(false),
56 releaseEvent(this), dequeueEvent(this)
57{
58}
59
60void
61SimpleMemory::init()
62{
63 AbstractMemory::init();
64
65 // allow unconnected memories as this is used in several ruby
66 // systems at the moment
67 if (port.isConnected()) {
68 port.sendRangeChange();
69 }
70}
71
72Tick
73SimpleMemory::recvAtomic(PacketPtr pkt)
74{
75 panic_if(pkt->cacheResponding(), "Should not see packets where cache "
76 "is responding");
77
78 access(pkt);
79 return getLatency();
80}
81
82void
83SimpleMemory::recvFunctional(PacketPtr pkt)
84{
85 pkt->pushLabel(name());
86
87 functionalAccess(pkt);
88
89 bool done = false;
90 auto p = packetQueue.begin();
91 // potentially update the packets in our packet queue as well
92 while (!done && p != packetQueue.end()) {
93 done = pkt->checkFunctional(p->pkt);
94 ++p;
95 }
96
97 pkt->popLabel();
98}
99
100bool
101SimpleMemory::recvTimingReq(PacketPtr pkt)
102{
103 panic_if(pkt->cacheResponding(), "Should not see packets where cache "
104 "is responding");
105
106 panic_if(!(pkt->isRead() || pkt->isWrite()),
107 "Should only see read and writes at memory controller, "
108 "saw %s to %#llx\n", pkt->cmdString(), pkt->getAddr());
109
110 // we should not get a new request after committing to retry the
111 // current one, but unfortunately the CPU violates this rule, so
112 // simply ignore it for now
113 if (retryReq)
114 return false;
115
116 // if we are busy with a read or write, remember that we have to
117 // retry
118 if (isBusy) {
119 retryReq = true;
120 return false;
121 }
122
123 // technically the packet only reaches us after the header delay,
124 // and since this is a memory controller we also need to
125 // deserialise the payload before performing any write operation
126 Tick receive_delay = pkt->headerDelay + pkt->payloadDelay;
127 pkt->headerDelay = pkt->payloadDelay = 0;
128
129 // update the release time according to the bandwidth limit, and
130 // do so with respect to the time it takes to finish this request
131 // rather than long term as it is the short term data rate that is
132 // limited for any real memory
133
134 // calculate an appropriate tick to release to not exceed
135 // the bandwidth limit
136 Tick duration = pkt->getSize() * bandwidth;
137
138 // only consider ourselves busy if there is any need to wait
139 // to avoid extra events being scheduled for (infinitely) fast
140 // memories
141 if (duration != 0) {
142 schedule(releaseEvent, curTick() + duration);
143 isBusy = true;
144 }
145
146 // go ahead and deal with the packet and put the response in the
147 // queue if there is one
148 bool needsResponse = pkt->needsResponse();
149 recvAtomic(pkt);
150 // turn packet around to go back to requester if response expected
151 if (needsResponse) {
152 // recvAtomic() should already have turned packet into
153 // atomic response
154 assert(pkt->isResponse());
155
156 Tick when_to_send = curTick() + receive_delay + getLatency();
157
158 // typically this should be added at the end, so start the
159 // insertion sort with the last element, also make sure not to
160 // re-order in front of some existing packet with the same
161 // address, the latter is important as this memory effectively
162 // hands out exclusive copies (shared is not asserted)
163 auto i = packetQueue.end();
164 --i;
165 while (i != packetQueue.begin() && when_to_send < i->tick &&
166 i->pkt->getAddr() != pkt->getAddr())
167 --i;
168
169 // emplace inserts the element before the position pointed to by
170 // the iterator, so advance it one step
171 packetQueue.emplace(++i, pkt, when_to_send);
172
173 if (!retryResp && !dequeueEvent.scheduled())
174 schedule(dequeueEvent, packetQueue.back().tick);
175 } else {
176 pendingDelete.reset(pkt);
177 }
178
179 return true;
180}
181
182void
183SimpleMemory::release()
184{
185 assert(isBusy);
186 isBusy = false;
187 if (retryReq) {
188 retryReq = false;
189 port.sendRetryReq();
190 }
191}
192
193void
194SimpleMemory::dequeue()
195{
196 assert(!packetQueue.empty());
197 DeferredPacket deferred_pkt = packetQueue.front();
198
199 retryResp = !port.sendTimingResp(deferred_pkt.pkt);
200
201 if (!retryResp) {
202 packetQueue.pop_front();
203
204 // if the queue is not empty, schedule the next dequeue event,
205 // otherwise signal that we are drained if we were asked to do so
206 if (!packetQueue.empty()) {
207 // if there were packets that got in-between then we
208 // already have an event scheduled, so use re-schedule
209 reschedule(dequeueEvent,
210 std::max(packetQueue.front().tick, curTick()), true);
211 } else if (drainState() == DrainState::Draining) {
212 DPRINTF(Drain, "Draining of SimpleMemory complete\n");
213 signalDrainDone();
214 }
215 }
216}
217
218Tick
219SimpleMemory::getLatency() const
220{
221 return latency +
222 (latency_var ? random_mt.random<Tick>(0, latency_var) : 0);
223}
224
225void
226SimpleMemory::recvRespRetry()
227{
228 assert(retryResp);
229
230 dequeue();
231}
232
233BaseSlavePort &
234SimpleMemory::getSlavePort(const std::string &if_name, PortID idx)
235{
236 if (if_name != "port") {
237 return MemObject::getSlavePort(if_name, idx);
238 } else {
239 return port;
240 }
241}
242
243DrainState
244SimpleMemory::drain()
245{
246 if (!packetQueue.empty()) {
247 DPRINTF(Drain, "SimpleMemory Queue has requests, waiting to drain\n");
248 return DrainState::Draining;
249 } else {
250 return DrainState::Drained;
251 }
252}
253
254SimpleMemory::MemoryPort::MemoryPort(const std::string& _name,
255 SimpleMemory& _memory)
256 : SlavePort(_name, &_memory), memory(_memory)
257{ }
258
259AddrRangeList
260SimpleMemory::MemoryPort::getAddrRanges() const
261{
262 AddrRangeList ranges;
263 ranges.push_back(memory.getAddrRange());
264 return ranges;
265}
266
267Tick
268SimpleMemory::MemoryPort::recvAtomic(PacketPtr pkt)
269{
270 return memory.recvAtomic(pkt);
271}
272
273void
274SimpleMemory::MemoryPort::recvFunctional(PacketPtr pkt)
275{
276 memory.recvFunctional(pkt);
277}
278
279bool
280SimpleMemory::MemoryPort::recvTimingReq(PacketPtr pkt)
281{
282 return memory.recvTimingReq(pkt);
283}
284
285void
286SimpleMemory::MemoryPort::recvRespRetry()
287{
288 memory.recvRespRetry();
289}
290
291SimpleMemory*
292SimpleMemoryParams::create()
293{
294 return new SimpleMemory(this);
295}
| 48#include "debug/Drain.hh"
49
50using namespace std;
51
52SimpleMemory::SimpleMemory(const SimpleMemoryParams* p) :
53 AbstractMemory(p),
54 port(name() + ".port", *this), latency(p->latency),
55 latency_var(p->latency_var), bandwidth(p->bandwidth), isBusy(false),
56 retryReq(false), retryResp(false),
57 releaseEvent(this), dequeueEvent(this)
58{
59}
60
61void
62SimpleMemory::init()
63{
64 AbstractMemory::init();
65
66 // allow unconnected memories as this is used in several ruby
67 // systems at the moment
68 if (port.isConnected()) {
69 port.sendRangeChange();
70 }
71}
72
73Tick
74SimpleMemory::recvAtomic(PacketPtr pkt)
75{
76 panic_if(pkt->cacheResponding(), "Should not see packets where cache "
77 "is responding");
78
79 access(pkt);
80 return getLatency();
81}
82
83void
84SimpleMemory::recvFunctional(PacketPtr pkt)
85{
86 pkt->pushLabel(name());
87
88 functionalAccess(pkt);
89
90 bool done = false;
91 auto p = packetQueue.begin();
92 // potentially update the packets in our packet queue as well
93 while (!done && p != packetQueue.end()) {
94 done = pkt->checkFunctional(p->pkt);
95 ++p;
96 }
97
98 pkt->popLabel();
99}
100
101bool
102SimpleMemory::recvTimingReq(PacketPtr pkt)
103{
104 panic_if(pkt->cacheResponding(), "Should not see packets where cache "
105 "is responding");
106
107 panic_if(!(pkt->isRead() || pkt->isWrite()),
108 "Should only see read and writes at memory controller, "
109 "saw %s to %#llx\n", pkt->cmdString(), pkt->getAddr());
110
111 // we should not get a new request after committing to retry the
112 // current one, but unfortunately the CPU violates this rule, so
113 // simply ignore it for now
114 if (retryReq)
115 return false;
116
117 // if we are busy with a read or write, remember that we have to
118 // retry
119 if (isBusy) {
120 retryReq = true;
121 return false;
122 }
123
124 // technically the packet only reaches us after the header delay,
125 // and since this is a memory controller we also need to
126 // deserialise the payload before performing any write operation
127 Tick receive_delay = pkt->headerDelay + pkt->payloadDelay;
128 pkt->headerDelay = pkt->payloadDelay = 0;
129
130 // update the release time according to the bandwidth limit, and
131 // do so with respect to the time it takes to finish this request
132 // rather than long term as it is the short term data rate that is
133 // limited for any real memory
134
135 // calculate an appropriate tick to release to not exceed
136 // the bandwidth limit
137 Tick duration = pkt->getSize() * bandwidth;
138
139 // only consider ourselves busy if there is any need to wait
140 // to avoid extra events being scheduled for (infinitely) fast
141 // memories
142 if (duration != 0) {
143 schedule(releaseEvent, curTick() + duration);
144 isBusy = true;
145 }
146
147 // go ahead and deal with the packet and put the response in the
148 // queue if there is one
149 bool needsResponse = pkt->needsResponse();
150 recvAtomic(pkt);
151 // turn packet around to go back to requester if response expected
152 if (needsResponse) {
153 // recvAtomic() should already have turned packet into
154 // atomic response
155 assert(pkt->isResponse());
156
157 Tick when_to_send = curTick() + receive_delay + getLatency();
158
159 // typically this should be added at the end, so start the
160 // insertion sort with the last element, also make sure not to
161 // re-order in front of some existing packet with the same
162 // address, the latter is important as this memory effectively
163 // hands out exclusive copies (shared is not asserted)
164 auto i = packetQueue.end();
165 --i;
166 while (i != packetQueue.begin() && when_to_send < i->tick &&
167 i->pkt->getAddr() != pkt->getAddr())
168 --i;
169
170 // emplace inserts the element before the position pointed to by
171 // the iterator, so advance it one step
172 packetQueue.emplace(++i, pkt, when_to_send);
173
174 if (!retryResp && !dequeueEvent.scheduled())
175 schedule(dequeueEvent, packetQueue.back().tick);
176 } else {
177 pendingDelete.reset(pkt);
178 }
179
180 return true;
181}
182
183void
184SimpleMemory::release()
185{
186 assert(isBusy);
187 isBusy = false;
188 if (retryReq) {
189 retryReq = false;
190 port.sendRetryReq();
191 }
192}
193
194void
195SimpleMemory::dequeue()
196{
197 assert(!packetQueue.empty());
198 DeferredPacket deferred_pkt = packetQueue.front();
199
200 retryResp = !port.sendTimingResp(deferred_pkt.pkt);
201
202 if (!retryResp) {
203 packetQueue.pop_front();
204
205 // if the queue is not empty, schedule the next dequeue event,
206 // otherwise signal that we are drained if we were asked to do so
207 if (!packetQueue.empty()) {
208 // if there were packets that got in-between then we
209 // already have an event scheduled, so use re-schedule
210 reschedule(dequeueEvent,
211 std::max(packetQueue.front().tick, curTick()), true);
212 } else if (drainState() == DrainState::Draining) {
213 DPRINTF(Drain, "Draining of SimpleMemory complete\n");
214 signalDrainDone();
215 }
216 }
217}
218
219Tick
220SimpleMemory::getLatency() const
221{
222 return latency +
223 (latency_var ? random_mt.random<Tick>(0, latency_var) : 0);
224}
225
226void
227SimpleMemory::recvRespRetry()
228{
229 assert(retryResp);
230
231 dequeue();
232}
233
234BaseSlavePort &
235SimpleMemory::getSlavePort(const std::string &if_name, PortID idx)
236{
237 if (if_name != "port") {
238 return MemObject::getSlavePort(if_name, idx);
239 } else {
240 return port;
241 }
242}
243
244DrainState
245SimpleMemory::drain()
246{
247 if (!packetQueue.empty()) {
248 DPRINTF(Drain, "SimpleMemory Queue has requests, waiting to drain\n");
249 return DrainState::Draining;
250 } else {
251 return DrainState::Drained;
252 }
253}
254
255SimpleMemory::MemoryPort::MemoryPort(const std::string& _name,
256 SimpleMemory& _memory)
257 : SlavePort(_name, &_memory), memory(_memory)
258{ }
259
260AddrRangeList
261SimpleMemory::MemoryPort::getAddrRanges() const
262{
263 AddrRangeList ranges;
264 ranges.push_back(memory.getAddrRange());
265 return ranges;
266}
267
268Tick
269SimpleMemory::MemoryPort::recvAtomic(PacketPtr pkt)
270{
271 return memory.recvAtomic(pkt);
272}
273
274void
275SimpleMemory::MemoryPort::recvFunctional(PacketPtr pkt)
276{
277 memory.recvFunctional(pkt);
278}
279
280bool
281SimpleMemory::MemoryPort::recvTimingReq(PacketPtr pkt)
282{
283 return memory.recvTimingReq(pkt);
284}
285
286void
287SimpleMemory::MemoryPort::recvRespRetry()
288{
289 memory.recvRespRetry();
290}
291
292SimpleMemory*
293SimpleMemoryParams::create()
294{
295 return new SimpleMemory(this);
296}
|