1/*
2 * Copyright (c) 2010-2013 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2001-2005 The Regents of The University of Michigan
15 * All rights reserved.
16 *
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions are
19 * met: redistributions of source code must retain the above copyright
20 * notice, this list of conditions and the following disclaimer;
21 * redistributions in binary form must reproduce the above copyright
22 * notice, this list of conditions and the following disclaimer in the
23 * documentation and/or other materials provided with the distribution;
24 * neither the name of the copyright holders nor the names of its
25 * contributors may be used to endorse or promote products derived from
26 * this software without specific prior written permission.
27 *
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 *
40 * Authors: Ron Dreslinski
41 * Ali Saidi
42 * Andreas Hansson
43 */
44
45#include "base/random.hh"
46#include "mem/simple_mem.hh"
47#include "debug/Drain.hh"
48
49using namespace std;
50
51SimpleMemory::SimpleMemory(const SimpleMemoryParams* p) :
52 AbstractMemory(p),
53 port(name() + ".port", *this), latency(p->latency),
54 latency_var(p->latency_var), bandwidth(p->bandwidth), isBusy(false),
55 retryReq(false), retryResp(false),
| 1/*
2 * Copyright (c) 2010-2013 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2001-2005 The Regents of The University of Michigan
15 * All rights reserved.
16 *
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions are
19 * met: redistributions of source code must retain the above copyright
20 * notice, this list of conditions and the following disclaimer;
21 * redistributions in binary form must reproduce the above copyright
22 * notice, this list of conditions and the following disclaimer in the
23 * documentation and/or other materials provided with the distribution;
24 * neither the name of the copyright holders nor the names of its
25 * contributors may be used to endorse or promote products derived from
26 * this software without specific prior written permission.
27 *
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 *
40 * Authors: Ron Dreslinski
41 * Ali Saidi
42 * Andreas Hansson
43 */
44
45#include "base/random.hh"
46#include "mem/simple_mem.hh"
47#include "debug/Drain.hh"
48
49using namespace std;
50
51SimpleMemory::SimpleMemory(const SimpleMemoryParams* p) :
52 AbstractMemory(p),
53 port(name() + ".port", *this), latency(p->latency),
54 latency_var(p->latency_var), bandwidth(p->bandwidth), isBusy(false),
55 retryReq(false), retryResp(false),
|
56 releaseEvent(this), dequeueEvent(this), drainManager(NULL)
| 56 releaseEvent(this), dequeueEvent(this)
|
57{
58}
59
60void
61SimpleMemory::init()
62{
63 AbstractMemory::init();
64
65 // allow unconnected memories as this is used in several ruby
66 // systems at the moment
67 if (port.isConnected()) {
68 port.sendRangeChange();
69 }
70}
71
72Tick
73SimpleMemory::recvAtomic(PacketPtr pkt)
74{
75 access(pkt);
76 return pkt->memInhibitAsserted() ? 0 : getLatency();
77}
78
79void
80SimpleMemory::recvFunctional(PacketPtr pkt)
81{
82 pkt->pushLabel(name());
83
84 functionalAccess(pkt);
85
86 bool done = false;
87 auto p = packetQueue.begin();
88 // potentially update the packets in our packet queue as well
89 while (!done && p != packetQueue.end()) {
90 done = pkt->checkFunctional(p->pkt);
91 ++p;
92 }
93
94 pkt->popLabel();
95}
96
97bool
98SimpleMemory::recvTimingReq(PacketPtr pkt)
99{
100 /// @todo temporary hack to deal with memory corruption issues until
101 /// 4-phase transactions are complete
102 for (int x = 0; x < pendingDelete.size(); x++)
103 delete pendingDelete[x];
104 pendingDelete.clear();
105
106 if (pkt->memInhibitAsserted()) {
107 // snooper will supply based on copy of packet
108 // still target's responsibility to delete packet
109 pendingDelete.push_back(pkt);
110 return true;
111 }
112
113 // we should never get a new request after committing to retry the
114 // current one, the bus violates the rule as it simply sends a
115 // retry to the next one waiting on the retry list, so simply
116 // ignore it
117 if (retryReq)
118 return false;
119
120 // if we are busy with a read or write, remember that we have to
121 // retry
122 if (isBusy) {
123 retryReq = true;
124 return false;
125 }
126
127 // @todo someone should pay for this
128 pkt->headerDelay = pkt->payloadDelay = 0;
129
130 // update the release time according to the bandwidth limit, and
131 // do so with respect to the time it takes to finish this request
132 // rather than long term as it is the short term data rate that is
133 // limited for any real memory
134
135 // only look at reads and writes when determining if we are busy,
136 // and for how long, as it is not clear what to regulate for the
137 // other types of commands
138 if (pkt->isRead() || pkt->isWrite()) {
139 // calculate an appropriate tick to release to not exceed
140 // the bandwidth limit
141 Tick duration = pkt->getSize() * bandwidth;
142
143 // only consider ourselves busy if there is any need to wait
144 // to avoid extra events being scheduled for (infinitely) fast
145 // memories
146 if (duration != 0) {
147 schedule(releaseEvent, curTick() + duration);
148 isBusy = true;
149 }
150 }
151
152 // go ahead and deal with the packet and put the response in the
153 // queue if there is one
154 bool needsResponse = pkt->needsResponse();
155 recvAtomic(pkt);
156 // turn packet around to go back to requester if response expected
157 if (needsResponse) {
158 // recvAtomic() should already have turned packet into
159 // atomic response
160 assert(pkt->isResponse());
161 // to keep things simple (and in order), we put the packet at
162 // the end even if the latency suggests it should be sent
163 // before the packet(s) before it
164 packetQueue.emplace_back(DeferredPacket(pkt, curTick() + getLatency()));
165 if (!retryResp && !dequeueEvent.scheduled())
166 schedule(dequeueEvent, packetQueue.back().tick);
167 } else {
168 pendingDelete.push_back(pkt);
169 }
170
171 return true;
172}
173
174void
175SimpleMemory::release()
176{
177 assert(isBusy);
178 isBusy = false;
179 if (retryReq) {
180 retryReq = false;
181 port.sendRetryReq();
182 }
183}
184
185void
186SimpleMemory::dequeue()
187{
188 assert(!packetQueue.empty());
189 DeferredPacket deferred_pkt = packetQueue.front();
190
191 retryResp = !port.sendTimingResp(deferred_pkt.pkt);
192
193 if (!retryResp) {
194 packetQueue.pop_front();
195
196 // if the queue is not empty, schedule the next dequeue event,
197 // otherwise signal that we are drained if we were asked to do so
198 if (!packetQueue.empty()) {
199 // if there were packets that got in-between then we
200 // already have an event scheduled, so use re-schedule
201 reschedule(dequeueEvent,
202 std::max(packetQueue.front().tick, curTick()), true);
| 57{
58}
59
60void
61SimpleMemory::init()
62{
63 AbstractMemory::init();
64
65 // allow unconnected memories as this is used in several ruby
66 // systems at the moment
67 if (port.isConnected()) {
68 port.sendRangeChange();
69 }
70}
71
72Tick
73SimpleMemory::recvAtomic(PacketPtr pkt)
74{
75 access(pkt);
76 return pkt->memInhibitAsserted() ? 0 : getLatency();
77}
78
79void
80SimpleMemory::recvFunctional(PacketPtr pkt)
81{
82 pkt->pushLabel(name());
83
84 functionalAccess(pkt);
85
86 bool done = false;
87 auto p = packetQueue.begin();
88 // potentially update the packets in our packet queue as well
89 while (!done && p != packetQueue.end()) {
90 done = pkt->checkFunctional(p->pkt);
91 ++p;
92 }
93
94 pkt->popLabel();
95}
96
97bool
98SimpleMemory::recvTimingReq(PacketPtr pkt)
99{
100 /// @todo temporary hack to deal with memory corruption issues until
101 /// 4-phase transactions are complete
102 for (int x = 0; x < pendingDelete.size(); x++)
103 delete pendingDelete[x];
104 pendingDelete.clear();
105
106 if (pkt->memInhibitAsserted()) {
107 // snooper will supply based on copy of packet
108 // still target's responsibility to delete packet
109 pendingDelete.push_back(pkt);
110 return true;
111 }
112
113 // we should never get a new request after committing to retry the
114 // current one, the bus violates the rule as it simply sends a
115 // retry to the next one waiting on the retry list, so simply
116 // ignore it
117 if (retryReq)
118 return false;
119
120 // if we are busy with a read or write, remember that we have to
121 // retry
122 if (isBusy) {
123 retryReq = true;
124 return false;
125 }
126
127 // @todo someone should pay for this
128 pkt->headerDelay = pkt->payloadDelay = 0;
129
130 // update the release time according to the bandwidth limit, and
131 // do so with respect to the time it takes to finish this request
132 // rather than long term as it is the short term data rate that is
133 // limited for any real memory
134
135 // only look at reads and writes when determining if we are busy,
136 // and for how long, as it is not clear what to regulate for the
137 // other types of commands
138 if (pkt->isRead() || pkt->isWrite()) {
139 // calculate an appropriate tick to release to not exceed
140 // the bandwidth limit
141 Tick duration = pkt->getSize() * bandwidth;
142
143 // only consider ourselves busy if there is any need to wait
144 // to avoid extra events being scheduled for (infinitely) fast
145 // memories
146 if (duration != 0) {
147 schedule(releaseEvent, curTick() + duration);
148 isBusy = true;
149 }
150 }
151
152 // go ahead and deal with the packet and put the response in the
153 // queue if there is one
154 bool needsResponse = pkt->needsResponse();
155 recvAtomic(pkt);
156 // turn packet around to go back to requester if response expected
157 if (needsResponse) {
158 // recvAtomic() should already have turned packet into
159 // atomic response
160 assert(pkt->isResponse());
161 // to keep things simple (and in order), we put the packet at
162 // the end even if the latency suggests it should be sent
163 // before the packet(s) before it
164 packetQueue.emplace_back(DeferredPacket(pkt, curTick() + getLatency()));
165 if (!retryResp && !dequeueEvent.scheduled())
166 schedule(dequeueEvent, packetQueue.back().tick);
167 } else {
168 pendingDelete.push_back(pkt);
169 }
170
171 return true;
172}
173
174void
175SimpleMemory::release()
176{
177 assert(isBusy);
178 isBusy = false;
179 if (retryReq) {
180 retryReq = false;
181 port.sendRetryReq();
182 }
183}
184
185void
186SimpleMemory::dequeue()
187{
188 assert(!packetQueue.empty());
189 DeferredPacket deferred_pkt = packetQueue.front();
190
191 retryResp = !port.sendTimingResp(deferred_pkt.pkt);
192
193 if (!retryResp) {
194 packetQueue.pop_front();
195
196 // if the queue is not empty, schedule the next dequeue event,
197 // otherwise signal that we are drained if we were asked to do so
198 if (!packetQueue.empty()) {
199 // if there were packets that got in-between then we
200 // already have an event scheduled, so use re-schedule
201 reschedule(dequeueEvent,
202 std::max(packetQueue.front().tick, curTick()), true);
|
203 } else if (drainManager) {
204 DPRINTF(Drain, "Drainng of SimpleMemory complete\n");
205 drainManager->signalDrainDone();
206 drainManager = NULL;
| 203 } else if (drainState() == DrainState::Draining) {
204 DPRINTF(Drain, "Draining of SimpleMemory complete\n");
205 signalDrainDone();
|
207 }
208 }
209}
210
211Tick
212SimpleMemory::getLatency() const
213{
214 return latency +
215 (latency_var ? random_mt.random<Tick>(0, latency_var) : 0);
216}
217
218void
219SimpleMemory::recvRespRetry()
220{
221 assert(retryResp);
222
223 dequeue();
224}
225
226BaseSlavePort &
227SimpleMemory::getSlavePort(const std::string &if_name, PortID idx)
228{
229 if (if_name != "port") {
230 return MemObject::getSlavePort(if_name, idx);
231 } else {
232 return port;
233 }
234}
235
| 206 }
207 }
208}
209
210Tick
211SimpleMemory::getLatency() const
212{
213 return latency +
214 (latency_var ? random_mt.random<Tick>(0, latency_var) : 0);
215}
216
217void
218SimpleMemory::recvRespRetry()
219{
220 assert(retryResp);
221
222 dequeue();
223}
224
225BaseSlavePort &
226SimpleMemory::getSlavePort(const std::string &if_name, PortID idx)
227{
228 if (if_name != "port") {
229 return MemObject::getSlavePort(if_name, idx);
230 } else {
231 return port;
232 }
233}
234
|
236unsigned int
237SimpleMemory::drain(DrainManager *dm)
| 235DrainState
236SimpleMemory::drain()
|
238{
| 237{
|
239 int count = 0;
240
241 // also track our internal queue
| |
242 if (!packetQueue.empty()) {
| 238 if (!packetQueue.empty()) {
|
243 count += 1;
244 drainManager = dm;
| |
245 DPRINTF(Drain, "SimpleMemory Queue has requests, waiting to drain\n");
| 239 DPRINTF(Drain, "SimpleMemory Queue has requests, waiting to drain\n");
|
246 }
247
248 if (count)
249 setDrainState(DrainState::Draining);
250 else
251 setDrainState(DrainState::Drained);
252 return count;
| 240 return DrainState::Draining;
241 } else {
242 return DrainState::Drained;
243 }
|
253}
254
255SimpleMemory::MemoryPort::MemoryPort(const std::string& _name,
256 SimpleMemory& _memory)
257 : SlavePort(_name, &_memory), memory(_memory)
258{ }
259
260AddrRangeList
261SimpleMemory::MemoryPort::getAddrRanges() const
262{
263 AddrRangeList ranges;
264 ranges.push_back(memory.getAddrRange());
265 return ranges;
266}
267
268Tick
269SimpleMemory::MemoryPort::recvAtomic(PacketPtr pkt)
270{
271 return memory.recvAtomic(pkt);
272}
273
274void
275SimpleMemory::MemoryPort::recvFunctional(PacketPtr pkt)
276{
277 memory.recvFunctional(pkt);
278}
279
280bool
281SimpleMemory::MemoryPort::recvTimingReq(PacketPtr pkt)
282{
283 return memory.recvTimingReq(pkt);
284}
285
286void
287SimpleMemory::MemoryPort::recvRespRetry()
288{
289 memory.recvRespRetry();
290}
291
292SimpleMemory*
293SimpleMemoryParams::create()
294{
295 return new SimpleMemory(this);
296}
| 244}
245
246SimpleMemory::MemoryPort::MemoryPort(const std::string& _name,
247 SimpleMemory& _memory)
248 : SlavePort(_name, &_memory), memory(_memory)
249{ }
250
251AddrRangeList
252SimpleMemory::MemoryPort::getAddrRanges() const
253{
254 AddrRangeList ranges;
255 ranges.push_back(memory.getAddrRange());
256 return ranges;
257}
258
259Tick
260SimpleMemory::MemoryPort::recvAtomic(PacketPtr pkt)
261{
262 return memory.recvAtomic(pkt);
263}
264
265void
266SimpleMemory::MemoryPort::recvFunctional(PacketPtr pkt)
267{
268 memory.recvFunctional(pkt);
269}
270
271bool
272SimpleMemory::MemoryPort::recvTimingReq(PacketPtr pkt)
273{
274 return memory.recvTimingReq(pkt);
275}
276
277void
278SimpleMemory::MemoryPort::recvRespRetry()
279{
280 memory.recvRespRetry();
281}
282
283SimpleMemory*
284SimpleMemoryParams::create()
285{
286 return new SimpleMemory(this);
287}
|