simple_mem.cc (9549:95a536fae9ac) | simple_mem.cc (9823:c8dd3368c6ba) |
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1/* | 1/* |
2 * Copyright (c) 2010-2012 ARM Limited | 2 * Copyright (c) 2010-2013 ARM Limited |
3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software 9 * licensed hereunder. You may use the software subject to the license 10 * terms below provided that you ensure that this notice is replicated --- 33 unchanged lines hidden (view full) --- 44 45#include "base/random.hh" 46#include "mem/simple_mem.hh" 47 48using namespace std; 49 50SimpleMemory::SimpleMemory(const SimpleMemoryParams* p) : 51 AbstractMemory(p), | 3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software 9 * licensed hereunder. You may use the software subject to the license 10 * terms below provided that you ensure that this notice is replicated --- 33 unchanged lines hidden (view full) --- 44 45#include "base/random.hh" 46#include "mem/simple_mem.hh" 47 48using namespace std; 49 50SimpleMemory::SimpleMemory(const SimpleMemoryParams* p) : 51 AbstractMemory(p), |
52 port(name() + ".port", *this), lat(p->latency), 53 lat_var(p->latency_var), bandwidth(p->bandwidth), 54 isBusy(false), retryReq(false), releaseEvent(this) | 52 port(name() + ".port", *this), latency(p->latency), 53 latency_var(p->latency_var), bandwidth(p->bandwidth), isBusy(false), 54 retryReq(false), retryResp(false), 55 releaseEvent(this), dequeueEvent(this), drainManager(NULL) |
55{ 56} 57 58void 59SimpleMemory::init() 60{ 61 // allow unconnected memories as this is used in several ruby 62 // systems at the moment 63 if (port.isConnected()) { 64 port.sendRangeChange(); 65 } 66} 67 68Tick | 56{ 57} 58 59void 60SimpleMemory::init() 61{ 62 // allow unconnected memories as this is used in several ruby 63 // systems at the moment 64 if (port.isConnected()) { 65 port.sendRangeChange(); 66 } 67} 68 69Tick |
69SimpleMemory::calculateLatency(PacketPtr pkt) | 70SimpleMemory::recvAtomic(PacketPtr pkt) |
70{ | 71{ |
71 if (pkt->memInhibitAsserted()) { 72 return 0; 73 } else { 74 Tick latency = lat; 75 if (lat_var != 0) 76 latency += random_mt.random<Tick>(0, lat_var); 77 return latency; 78 } 79} 80 81Tick 82SimpleMemory::doAtomicAccess(PacketPtr pkt) 83{ | |
84 access(pkt); | 72 access(pkt); |
85 return calculateLatency(pkt); | 73 return pkt->memInhibitAsserted() ? 0 : getLatency(); |
86} 87 88void | 74} 75 76void |
89SimpleMemory::doFunctionalAccess(PacketPtr pkt) | 77SimpleMemory::recvFunctional(PacketPtr pkt) |
90{ | 78{ |
79 pkt->pushLabel(name()); 80 |
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91 functionalAccess(pkt); | 81 functionalAccess(pkt); |
82 83 // potentially update the packets in our packet queue as well 84 for (auto i = packetQueue.begin(); i != packetQueue.end(); ++i) 85 pkt->checkFunctional(i->pkt); 86 87 pkt->popLabel(); |
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92} 93 94bool 95SimpleMemory::recvTimingReq(PacketPtr pkt) 96{ 97 /// @todo temporary hack to deal with memory corruption issues until 98 /// 4-phase transactions are complete 99 for (int x = 0; x < pendingDelete.size(); x++) --- 44 unchanged lines hidden (view full) --- 144 schedule(releaseEvent, curTick() + duration); 145 isBusy = true; 146 } 147 } 148 149 // go ahead and deal with the packet and put the response in the 150 // queue if there is one 151 bool needsResponse = pkt->needsResponse(); | 88} 89 90bool 91SimpleMemory::recvTimingReq(PacketPtr pkt) 92{ 93 /// @todo temporary hack to deal with memory corruption issues until 94 /// 4-phase transactions are complete 95 for (int x = 0; x < pendingDelete.size(); x++) --- 44 unchanged lines hidden (view full) --- 140 schedule(releaseEvent, curTick() + duration); 141 isBusy = true; 142 } 143 } 144 145 // go ahead and deal with the packet and put the response in the 146 // queue if there is one 147 bool needsResponse = pkt->needsResponse(); |
152 Tick latency = doAtomicAccess(pkt); | 148 recvAtomic(pkt); |
153 // turn packet around to go back to requester if response expected 154 if (needsResponse) { | 149 // turn packet around to go back to requester if response expected 150 if (needsResponse) { |
155 // doAtomicAccess() should already have turned packet into | 151 // recvAtomic() should already have turned packet into |
156 // atomic response 157 assert(pkt->isResponse()); | 152 // atomic response 153 assert(pkt->isResponse()); |
158 port.schedTimingResp(pkt, curTick() + latency); | 154 // to keep things simple (and in order), we put the packet at 155 // the end even if the latency suggests it should be sent 156 // before the packet(s) before it 157 packetQueue.push_back(DeferredPacket(pkt, curTick() + getLatency())); 158 if (!dequeueEvent.scheduled()) 159 schedule(dequeueEvent, packetQueue.back().tick); |
159 } else { 160 pendingDelete.push_back(pkt); 161 } 162 163 return true; 164} 165 166void 167SimpleMemory::release() 168{ 169 assert(isBusy); 170 isBusy = false; 171 if (retryReq) { 172 retryReq = false; 173 port.sendRetry(); 174 } 175} 176 | 160 } else { 161 pendingDelete.push_back(pkt); 162 } 163 164 return true; 165} 166 167void 168SimpleMemory::release() 169{ 170 assert(isBusy); 171 isBusy = false; 172 if (retryReq) { 173 retryReq = false; 174 port.sendRetry(); 175 } 176} 177 |
178void 179SimpleMemory::dequeue() 180{ 181 assert(!packetQueue.empty()); 182 DeferredPacket deferred_pkt = packetQueue.front(); 183 184 retryResp = !port.sendTimingResp(deferred_pkt.pkt); 185 186 if (!retryResp) { 187 packetQueue.pop_front(); 188 189 // if the queue is not empty, schedule the next dequeue event, 190 // otherwise signal that we are drained if we were asked to do so 191 if (!packetQueue.empty()) { 192 // if there were packets that got in-between then we 193 // already have an event scheduled, so use re-schedule 194 reschedule(dequeueEvent, 195 std::max(packetQueue.front().tick, curTick()), true); 196 } else if (drainManager) { 197 drainManager->signalDrainDone(); 198 drainManager = NULL; 199 } 200 } 201} 202 203Tick 204SimpleMemory::getLatency() const 205{ 206 return latency + 207 (latency_var ? random_mt.random<Tick>(0, latency_var) : 0); 208} 209 210void 211SimpleMemory::recvRetry() 212{ 213 assert(retryResp); 214 215 dequeue(); 216} 217 |
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177BaseSlavePort & 178SimpleMemory::getSlavePort(const std::string &if_name, PortID idx) 179{ 180 if (if_name != "port") { 181 return MemObject::getSlavePort(if_name, idx); 182 } else { 183 return port; 184 } 185} 186 187unsigned int 188SimpleMemory::drain(DrainManager *dm) 189{ | 218BaseSlavePort & 219SimpleMemory::getSlavePort(const std::string &if_name, PortID idx) 220{ 221 if (if_name != "port") { 222 return MemObject::getSlavePort(if_name, idx); 223 } else { 224 return port; 225 } 226} 227 228unsigned int 229SimpleMemory::drain(DrainManager *dm) 230{ |
190 int count = port.drain(dm); | 231 int count = 0; |
191 | 232 |
233 // also track our internal queue 234 if (!packetQueue.empty()) { 235 count += 1; 236 drainManager = dm; 237 } 238 |
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192 if (count) 193 setDrainState(Drainable::Draining); 194 else 195 setDrainState(Drainable::Drained); 196 return count; 197} 198 199SimpleMemory::MemoryPort::MemoryPort(const std::string& _name, 200 SimpleMemory& _memory) | 239 if (count) 240 setDrainState(Drainable::Draining); 241 else 242 setDrainState(Drainable::Drained); 243 return count; 244} 245 246SimpleMemory::MemoryPort::MemoryPort(const std::string& _name, 247 SimpleMemory& _memory) |
201 : QueuedSlavePort(_name, &_memory, queueImpl), 202 queueImpl(_memory, *this), memory(_memory) | 248 : SlavePort(_name, &_memory), memory(_memory) |
203{ } 204 205AddrRangeList 206SimpleMemory::MemoryPort::getAddrRanges() const 207{ 208 AddrRangeList ranges; 209 ranges.push_back(memory.getAddrRange()); 210 return ranges; 211} 212 213Tick 214SimpleMemory::MemoryPort::recvAtomic(PacketPtr pkt) 215{ | 249{ } 250 251AddrRangeList 252SimpleMemory::MemoryPort::getAddrRanges() const 253{ 254 AddrRangeList ranges; 255 ranges.push_back(memory.getAddrRange()); 256 return ranges; 257} 258 259Tick 260SimpleMemory::MemoryPort::recvAtomic(PacketPtr pkt) 261{ |
216 return memory.doAtomicAccess(pkt); | 262 return memory.recvAtomic(pkt); |
217} 218 219void 220SimpleMemory::MemoryPort::recvFunctional(PacketPtr pkt) 221{ | 263} 264 265void 266SimpleMemory::MemoryPort::recvFunctional(PacketPtr pkt) 267{ |
222 pkt->pushLabel(memory.name()); 223 224 if (!queue.checkFunctional(pkt)) { 225 // Default implementation of SimpleTimingPort::recvFunctional() 226 // calls recvAtomic() and throws away the latency; we can save a 227 // little here by just not calculating the latency. 228 memory.doFunctionalAccess(pkt); 229 } 230 231 pkt->popLabel(); | 268 memory.recvFunctional(pkt); |
232} 233 234bool 235SimpleMemory::MemoryPort::recvTimingReq(PacketPtr pkt) 236{ 237 return memory.recvTimingReq(pkt); 238} 239 | 269} 270 271bool 272SimpleMemory::MemoryPort::recvTimingReq(PacketPtr pkt) 273{ 274 return memory.recvTimingReq(pkt); 275} 276 |
277void 278SimpleMemory::MemoryPort::recvRetry() 279{ 280 memory.recvRetry(); 281} 282 |
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240SimpleMemory* 241SimpleMemoryParams::create() 242{ 243 return new SimpleMemory(this); 244} | 283SimpleMemory* 284SimpleMemoryParams::create() 285{ 286 return new SimpleMemory(this); 287} |