1/*
2 * Copyright (c) 2011-2013, 2018 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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65 * This object is a proxy for a structural port, to be used for debug
66 * accesses to secure memory.
67 *
68 * The addresses are interpreted as physical addresses to secure memory.
69 */
70class SecurePortProxy : public PortProxy
71{
72 public:
73 SecurePortProxy(MasterPort &port, unsigned int cache_line_size)
74 : PortProxy(port, cache_line_size) {}
75
76 bool tryReadBlob(Addr addr, void *p, int size) const override;
77 bool tryWriteBlob(Addr addr, const void *p, int size) const override;
78 bool tryMemsetBlob(Addr addr, uint8_t val, int size) const override;
79};
80
81#endif // __MEM_SECURE_PORT_PROXY_HH__