1/* 2 * Copyright (c) 2011 ARM Limited 3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software 9 * licensed hereunder. You may use the software subject to the license 10 * terms below provided that you ensure that this notice is replicated 11 * unmodified and in its entirety in all distributions of the software, 12 * modified or unmodified, in source code or in binary form. 13 * 14 * Copyright (c) 2001-2005 The Regents of The University of Michigan 15 * All rights reserved. 16 * 17 * Redistribution and use in source and binary forms, with or without 18 * modification, are permitted provided that the following conditions are 19 * met: redistributions of source code must retain the above copyright 20 * notice, this list of conditions and the following disclaimer; 21 * redistributions in binary form must reproduce the above copyright 22 * notice, this list of conditions and the following disclaimer in the 23 * documentation and/or other materials provided with the distribution; 24 * neither the name of the copyright holders nor the names of its 25 * contributors may be used to endorse or promote products derived from 26 * this software without specific prior written permission. 27 * 28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 39 * 40 * Authors: Ron Dreslinski 41 * Steve Reinhardt 42 * Andreas Hansson 43 */ 44 45#include "mem/se_translating_port_proxy.hh" 46 47#include <string> 48 49#include "arch/isa_traits.hh" 50#include "base/chunk_generator.hh" 51#include "config/the_isa.hh" 52#include "mem/page_table.hh" 53#include "sim/process.hh" 54#include "sim/system.hh" 55 56using namespace TheISA; 57 58SETranslatingPortProxy::SETranslatingPortProxy(MasterPort& port, Process *p, 59 AllocType alloc) 60 : PortProxy(port, p->system->cacheLineSize()), pTable(p->pTable), 61 process(p), allocating(alloc) 62{ } 63 |
64bool 65SETranslatingPortProxy::tryReadBlob(Addr addr, uint8_t *p, int size) const 66{ 67 int prevSize = 0; 68 69 for (ChunkGenerator gen(addr, size, PageBytes); !gen.done(); gen.next()) { 70 Addr paddr; 71 72 if (!pTable->translate(gen.addr(),paddr)) 73 return false; 74 75 PortProxy::readBlobPhys(paddr, 0, p + prevSize, gen.size()); 76 prevSize += gen.size(); 77 } 78 79 return true; 80} 81 |
82 |
83bool 84SETranslatingPortProxy::tryWriteBlob(Addr addr, const uint8_t *p, 85 int size) const 86{ 87 int prevSize = 0; 88 89 for (ChunkGenerator gen(addr, size, PageBytes); !gen.done(); gen.next()) { 90 Addr paddr; 91 92 if (!pTable->translate(gen.addr(), paddr)) { 93 if (allocating == Always) { 94 process->allocateMem(roundDown(gen.addr(), PageBytes), 95 PageBytes); 96 } else if (allocating == NextPage) { 97 // check if we've accessed the next page on the stack 98 if (!process->fixupStackFault(gen.addr())) 99 panic("Page table fault when accessing virtual address %#x " 100 "during functional write\n", gen.addr()); 101 } else { 102 return false; 103 } 104 pTable->translate(gen.addr(), paddr); 105 } 106 107 PortProxy::writeBlobPhys(paddr, 0, p + prevSize, gen.size()); 108 prevSize += gen.size(); 109 } 110 111 return true; 112} 113 114 |
115bool 116SETranslatingPortProxy::tryMemsetBlob(Addr addr, uint8_t val, int size) const 117{ 118 for (ChunkGenerator gen(addr, size, PageBytes); !gen.done(); gen.next()) { 119 Addr paddr; 120 121 if (!pTable->translate(gen.addr(), paddr)) { 122 if (allocating == Always) { 123 process->allocateMem(roundDown(gen.addr(), PageBytes), 124 PageBytes); 125 pTable->translate(gen.addr(), paddr); 126 } else { 127 return false; 128 } 129 } 130 131 PortProxy::memsetBlobPhys(paddr, 0, val, gen.size()); 132 } 133 134 return true; 135} |