1/*
2 * Copyright (c) 2011 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2001-2005 The Regents of The University of Michigan
15 * All rights reserved.
16 *
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions are
19 * met: redistributions of source code must retain the above copyright
20 * notice, this list of conditions and the following disclaimer;
21 * redistributions in binary form must reproduce the above copyright
22 * notice, this list of conditions and the following disclaimer in the
23 * documentation and/or other materials provided with the distribution;
24 * neither the name of the copyright holders nor the names of its
25 * contributors may be used to endorse or promote products derived from
26 * this software without specific prior written permission.
27 *
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 *
40 * Authors: Ron Dreslinski
41 * Steve Reinhardt
42 * Andreas Hansson
43 */
44
45#include "mem/se_translating_port_proxy.hh"
46
47#include <string>
48
49#include "arch/isa_traits.hh"
50#include "base/chunk_generator.hh"
51#include "config/the_isa.hh"
52#include "mem/page_table.hh"
53#include "sim/process.hh"
54#include "sim/system.hh"
55
56using namespace TheISA;
57
| 1/*
2 * Copyright (c) 2011 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2001-2005 The Regents of The University of Michigan
15 * All rights reserved.
16 *
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions are
19 * met: redistributions of source code must retain the above copyright
20 * notice, this list of conditions and the following disclaimer;
21 * redistributions in binary form must reproduce the above copyright
22 * notice, this list of conditions and the following disclaimer in the
23 * documentation and/or other materials provided with the distribution;
24 * neither the name of the copyright holders nor the names of its
25 * contributors may be used to endorse or promote products derived from
26 * this software without specific prior written permission.
27 *
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 *
40 * Authors: Ron Dreslinski
41 * Steve Reinhardt
42 * Andreas Hansson
43 */
44
45#include "mem/se_translating_port_proxy.hh"
46
47#include <string>
48
49#include "arch/isa_traits.hh"
50#include "base/chunk_generator.hh"
51#include "config/the_isa.hh"
52#include "mem/page_table.hh"
53#include "sim/process.hh"
54#include "sim/system.hh"
55
56using namespace TheISA;
57
|
58SETranslatingPortProxy::SETranslatingPortProxy(MasterPort& port, Process *p,
59 AllocType alloc)
| 58SETranslatingPortProxy::SETranslatingPortProxy(
59 SendFunctionalFunc func, Process *p, AllocType alloc)
60 : PortProxy(func, p->system->cacheLineSize()), pTable(p->pTable),
61 process(p), allocating(alloc)
62{ }
63SETranslatingPortProxy::SETranslatingPortProxy(MasterPort &port,
64 Process *p, AllocType alloc)
|
60 : PortProxy(port, p->system->cacheLineSize()), pTable(p->pTable),
61 process(p), allocating(alloc)
62{ }
63
64bool
65SETranslatingPortProxy::tryReadBlob(Addr addr, void *p, int size) const
66{
67 int prevSize = 0;
68 auto *bytes = static_cast<uint8_t *>(p);
69
70 for (ChunkGenerator gen(addr, size, PageBytes); !gen.done(); gen.next()) {
71 Addr paddr;
72
73 if (!pTable->translate(gen.addr(),paddr))
74 return false;
75
76 PortProxy::readBlobPhys(paddr, 0, bytes + prevSize, gen.size());
77 prevSize += gen.size();
78 }
79
80 return true;
81}
82
83
84bool
85SETranslatingPortProxy::tryWriteBlob(Addr addr, const void *p, int size) const
86{
87 int prevSize = 0;
88 auto *bytes = static_cast<const uint8_t *>(p);
89
90 for (ChunkGenerator gen(addr, size, PageBytes); !gen.done(); gen.next()) {
91 Addr paddr;
92
93 if (!pTable->translate(gen.addr(), paddr)) {
94 if (allocating == Always) {
95 process->allocateMem(roundDown(gen.addr(), PageBytes),
96 PageBytes);
97 } else if (allocating == NextPage) {
98 // check if we've accessed the next page on the stack
99 if (!process->fixupStackFault(gen.addr()))
100 panic("Page table fault when accessing virtual address %#x "
101 "during functional write\n", gen.addr());
102 } else {
103 return false;
104 }
105 pTable->translate(gen.addr(), paddr);
106 }
107
108 PortProxy::writeBlobPhys(paddr, 0, bytes + prevSize, gen.size());
109 prevSize += gen.size();
110 }
111
112 return true;
113}
114
115
116bool
117SETranslatingPortProxy::tryMemsetBlob(Addr addr, uint8_t val, int size) const
118{
119 for (ChunkGenerator gen(addr, size, PageBytes); !gen.done(); gen.next()) {
120 Addr paddr;
121
122 if (!pTable->translate(gen.addr(), paddr)) {
123 if (allocating == Always) {
124 process->allocateMem(roundDown(gen.addr(), PageBytes),
125 PageBytes);
126 pTable->translate(gen.addr(), paddr);
127 } else {
128 return false;
129 }
130 }
131
132 PortProxy::memsetBlobPhys(paddr, 0, val, gen.size());
133 }
134
135 return true;
136}
| 65 : PortProxy(port, p->system->cacheLineSize()), pTable(p->pTable),
66 process(p), allocating(alloc)
67{ }
68
69bool
70SETranslatingPortProxy::tryReadBlob(Addr addr, void *p, int size) const
71{
72 int prevSize = 0;
73 auto *bytes = static_cast<uint8_t *>(p);
74
75 for (ChunkGenerator gen(addr, size, PageBytes); !gen.done(); gen.next()) {
76 Addr paddr;
77
78 if (!pTable->translate(gen.addr(),paddr))
79 return false;
80
81 PortProxy::readBlobPhys(paddr, 0, bytes + prevSize, gen.size());
82 prevSize += gen.size();
83 }
84
85 return true;
86}
87
88
89bool
90SETranslatingPortProxy::tryWriteBlob(Addr addr, const void *p, int size) const
91{
92 int prevSize = 0;
93 auto *bytes = static_cast<const uint8_t *>(p);
94
95 for (ChunkGenerator gen(addr, size, PageBytes); !gen.done(); gen.next()) {
96 Addr paddr;
97
98 if (!pTable->translate(gen.addr(), paddr)) {
99 if (allocating == Always) {
100 process->allocateMem(roundDown(gen.addr(), PageBytes),
101 PageBytes);
102 } else if (allocating == NextPage) {
103 // check if we've accessed the next page on the stack
104 if (!process->fixupStackFault(gen.addr()))
105 panic("Page table fault when accessing virtual address %#x "
106 "during functional write\n", gen.addr());
107 } else {
108 return false;
109 }
110 pTable->translate(gen.addr(), paddr);
111 }
112
113 PortProxy::writeBlobPhys(paddr, 0, bytes + prevSize, gen.size());
114 prevSize += gen.size();
115 }
116
117 return true;
118}
119
120
121bool
122SETranslatingPortProxy::tryMemsetBlob(Addr addr, uint8_t val, int size) const
123{
124 for (ChunkGenerator gen(addr, size, PageBytes); !gen.done(); gen.next()) {
125 Addr paddr;
126
127 if (!pTable->translate(gen.addr(), paddr)) {
128 if (allocating == Always) {
129 process->allocateMem(roundDown(gen.addr(), PageBytes),
130 PageBytes);
131 pTable->translate(gen.addr(), paddr);
132 } else {
133 return false;
134 }
135 }
136
137 PortProxy::memsetBlobPhys(paddr, 0, val, gen.size());
138 }
139
140 return true;
141}
|