Sequencer.py (9184:a1a8f137b796) | Sequencer.py (9338:97b4a2be1e5b) |
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1# Copyright (c) 2009 Advanced Micro Devices, Inc. 2# All rights reserved. 3# 4# Redistribution and use in source and binary forms, with or without 5# modification, are permitted provided that the following conditions are 6# met: redistributions of source code must retain the above copyright 7# notice, this list of conditions and the following disclaimer; 8# redistributions in binary form must reproduce the above copyright --- 20 unchanged lines hidden (view full) --- 29 30from m5.params import * 31from m5.proxy import * 32from MemObject import MemObject 33 34class RubyPort(MemObject): 35 type = 'RubyPort' 36 abstract = True | 1# Copyright (c) 2009 Advanced Micro Devices, Inc. 2# All rights reserved. 3# 4# Redistribution and use in source and binary forms, with or without 5# modification, are permitted provided that the following conditions are 6# met: redistributions of source code must retain the above copyright 7# notice, this list of conditions and the following disclaimer; 8# redistributions in binary form must reproduce the above copyright --- 20 unchanged lines hidden (view full) --- 29 30from m5.params import * 31from m5.proxy import * 32from MemObject import MemObject 33 34class RubyPort(MemObject): 35 type = 'RubyPort' 36 abstract = True |
37 cxx_header = "mem/ruby/system/RubyPort.hh" |
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37 slave = VectorSlavePort("CPU slave port") 38 master = VectorMasterPort("CPU master port") 39 version = Param.Int(0, "") 40 pio_port = MasterPort("Ruby_pio_port") 41 using_ruby_tester = Param.Bool(False, "") 42 using_network_tester = Param.Bool(False, "") 43 access_phys_mem = Param.Bool(True, 44 "should the rubyport atomically update phys_mem") 45 ruby_system = Param.RubySystem("") 46 system = Param.System(Parent.any, "system object") 47 support_data_reqs = Param.Bool(True, "data cache requests supported") 48 support_inst_reqs = Param.Bool(True, "inst cache requests supported") 49 50 51class RubyPortProxy(RubyPort): 52 type = 'RubyPortProxy' | 38 slave = VectorSlavePort("CPU slave port") 39 master = VectorMasterPort("CPU master port") 40 version = Param.Int(0, "") 41 pio_port = MasterPort("Ruby_pio_port") 42 using_ruby_tester = Param.Bool(False, "") 43 using_network_tester = Param.Bool(False, "") 44 access_phys_mem = Param.Bool(True, 45 "should the rubyport atomically update phys_mem") 46 ruby_system = Param.RubySystem("") 47 system = Param.System(Parent.any, "system object") 48 support_data_reqs = Param.Bool(True, "data cache requests supported") 49 support_inst_reqs = Param.Bool(True, "inst cache requests supported") 50 51 52class RubyPortProxy(RubyPort): 53 type = 'RubyPortProxy' |
54 cxx_header = "mem/ruby/system/RubyPortProxy.hh" |
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53 54class RubySequencer(RubyPort): 55 type = 'RubySequencer' 56 cxx_class = 'Sequencer' | 55 56class RubySequencer(RubyPort): 57 type = 'RubySequencer' 58 cxx_class = 'Sequencer' |
59 cxx_header = "mem/ruby/system/Sequencer.hh" |
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57 icache = Param.RubyCache("") 58 dcache = Param.RubyCache("") 59 max_outstanding_requests = Param.Int(16, 60 "max requests (incl. prefetches) outstanding") 61 deadlock_threshold = Param.Cycles(500000, 62 "max outstanding cycles for a request before deadlock/livelock declared") 63 64class DMASequencer(RubyPort): 65 type = 'DMASequencer' | 60 icache = Param.RubyCache("") 61 dcache = Param.RubyCache("") 62 max_outstanding_requests = Param.Int(16, 63 "max requests (incl. prefetches) outstanding") 64 deadlock_threshold = Param.Cycles(500000, 65 "max outstanding cycles for a request before deadlock/livelock declared") 66 67class DMASequencer(RubyPort): 68 type = 'DMASequencer' |
69 cxx_header = "mem/ruby/system/DMASequencer.hh" |
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