Sequencer.py (8839:eeb293859255) Sequencer.py (8923:820111f58fbb)
1# Copyright (c) 2009 Advanced Micro Devices, Inc.
2# All rights reserved.
3#
4# Redistribution and use in source and binary forms, with or without
5# modification, are permitted provided that the following conditions are
6# met: redistributions of source code must retain the above copyright
7# notice, this list of conditions and the following disclaimer;
8# redistributions in binary form must reproduce the above copyright

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33
34class RubyPort(MemObject):
35 type = 'RubyPort'
36 abstract = True
37 slave = VectorSlavePort("CPU slave port")
38 master = VectorMasterPort("CPU master port")
39 version = Param.Int(0, "")
40 pio_port = MasterPort("Ruby_pio_port")
1# Copyright (c) 2009 Advanced Micro Devices, Inc.
2# All rights reserved.
3#
4# Redistribution and use in source and binary forms, with or without
5# modification, are permitted provided that the following conditions are
6# met: redistributions of source code must retain the above copyright
7# notice, this list of conditions and the following disclaimer;
8# redistributions in binary form must reproduce the above copyright

--- 24 unchanged lines hidden (view full) ---

33
34class RubyPort(MemObject):
35 type = 'RubyPort'
36 abstract = True
37 slave = VectorSlavePort("CPU slave port")
38 master = VectorMasterPort("CPU master port")
39 version = Param.Int(0, "")
40 pio_port = MasterPort("Ruby_pio_port")
41 physmem = Param.PhysicalMemory("")
42 physMemPort = MasterPort("port to physical memory")
43 using_ruby_tester = Param.Bool(False, "")
44 using_network_tester = Param.Bool(False, "")
45 access_phys_mem = Param.Bool(True,
46 "should the rubyport atomically update phys_mem")
47 ruby_system = Param.RubySystem("")
41 using_ruby_tester = Param.Bool(False, "")
42 using_network_tester = Param.Bool(False, "")
43 access_phys_mem = Param.Bool(True,
44 "should the rubyport atomically update phys_mem")
45 ruby_system = Param.RubySystem("")
46 system = Param.System(Parent.any, "system object")
48
49class RubyPortProxy(RubyPort):
50 type = 'RubyPortProxy'
51
52class RubySequencer(RubyPort):
53 type = 'RubySequencer'
54 cxx_class = 'Sequencer'
55 icache = Param.RubyCache("")
56 dcache = Param.RubyCache("")
57 max_outstanding_requests = Param.Int(16,
58 "max requests (incl. prefetches) outstanding")
59 deadlock_threshold = Param.Int(500000,
60 "max outstanding cycles for a request before deadlock/livelock declared")
61
62class DMASequencer(RubyPort):
63 type = 'DMASequencer'
47
48class RubyPortProxy(RubyPort):
49 type = 'RubyPortProxy'
50
51class RubySequencer(RubyPort):
52 type = 'RubySequencer'
53 cxx_class = 'Sequencer'
54 icache = Param.RubyCache("")
55 dcache = Param.RubyCache("")
56 max_outstanding_requests = Param.Int(16,
57 "max requests (incl. prefetches) outstanding")
58 deadlock_threshold = Param.Int(500000,
59 "max outstanding cycles for a request before deadlock/livelock declared")
60
61class DMASequencer(RubyPort):
62 type = 'DMASequencer'