Sequencer.py (7915:bc39c93a5519) | Sequencer.py (8171:19444b1f092c) |
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1# Copyright (c) 2009 Advanced Micro Devices, Inc. 2# All rights reserved. 3# 4# Redistribution and use in source and binary forms, with or without 5# modification, are permitted provided that the following conditions are 6# met: redistributions of source code must retain the above copyright 7# notice, this list of conditions and the following disclaimer; 8# redistributions in binary form must reproduce the above copyright --- 26 unchanged lines hidden (view full) --- 35 type = 'RubyPort' 36 abstract = True 37 port = VectorPort("M5 port") 38 version = Param.Int(0, "") 39 pio_port = Port("Ruby_pio_port") 40 physmem = Param.PhysicalMemory("") 41 physMemPort = Port("port to physical memory") 42 using_ruby_tester = Param.Bool(False, "") | 1# Copyright (c) 2009 Advanced Micro Devices, Inc. 2# All rights reserved. 3# 4# Redistribution and use in source and binary forms, with or without 5# modification, are permitted provided that the following conditions are 6# met: redistributions of source code must retain the above copyright 7# notice, this list of conditions and the following disclaimer; 8# redistributions in binary form must reproduce the above copyright --- 26 unchanged lines hidden (view full) --- 35 type = 'RubyPort' 36 abstract = True 37 port = VectorPort("M5 port") 38 version = Param.Int(0, "") 39 pio_port = Port("Ruby_pio_port") 40 physmem = Param.PhysicalMemory("") 41 physMemPort = Port("port to physical memory") 42 using_ruby_tester = Param.Bool(False, "") |
43 using_network_tester = Param.Bool(False, "") |
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43 access_phys_mem = Param.Bool(True, 44 "should the rubyport atomically update phys_mem") 45 46class RubySequencer(RubyPort): 47 type = 'RubySequencer' 48 cxx_class = 'Sequencer' 49 icache = Param.RubyCache("") 50 dcache = Param.RubyCache("") 51 max_outstanding_requests = Param.Int(16, 52 "max requests (incl. prefetches) outstanding") 53 deadlock_threshold = Param.Int(500000, 54 "max outstanding cycles for a request before deadlock/livelock declared") 55 56class DMASequencer(RubyPort): 57 type = 'DMASequencer' | 44 access_phys_mem = Param.Bool(True, 45 "should the rubyport atomically update phys_mem") 46 47class RubySequencer(RubyPort): 48 type = 'RubySequencer' 49 cxx_class = 'Sequencer' 50 icache = Param.RubyCache("") 51 dcache = Param.RubyCache("") 52 max_outstanding_requests = Param.Int(16, 53 "max requests (incl. prefetches) outstanding") 54 deadlock_threshold = Param.Int(500000, 55 "max outstanding cycles for a request before deadlock/livelock declared") 56 57class DMASequencer(RubyPort): 58 type = 'DMASequencer' |