Sequencer.py (6882:898047a3672c) Sequencer.py (6893:9cdf9b65d946)
1from m5.params import *
2from m5.proxy import *
3from MemObject import MemObject
4
5class RubyPort(MemObject):
6 type = 'RubyPort'
7 abstract = True
8 port = VectorPort("M5 port")
9 version = Param.Int(0, "")
10 pio_port = Port("Ruby_pio_port")
1from m5.params import *
2from m5.proxy import *
3from MemObject import MemObject
4
5class RubyPort(MemObject):
6 type = 'RubyPort'
7 abstract = True
8 port = VectorPort("M5 port")
9 version = Param.Int(0, "")
10 pio_port = Port("Ruby_pio_port")
11 physmem = Param.PhysicalMemory("")
12 physMemPort = Port("port to physical memory")
11
12class RubySequencer(RubyPort):
13 type = 'RubySequencer'
14 cxx_class = 'Sequencer'
15 icache = Param.RubyCache("")
16 dcache = Param.RubyCache("")
17 max_outstanding_requests = Param.Int(16,
18 "max requests (incl. prefetches) outstanding")
19 deadlock_threshold = Param.Int(500000,
20 "max outstanding cycles for a request before deadlock/livelock declared")
13
14class RubySequencer(RubyPort):
15 type = 'RubySequencer'
16 cxx_class = 'Sequencer'
17 icache = Param.RubyCache("")
18 dcache = Param.RubyCache("")
19 max_outstanding_requests = Param.Int(16,
20 "max requests (incl. prefetches) outstanding")
21 deadlock_threshold = Param.Int(500000,
22 "max outstanding cycles for a request before deadlock/livelock declared")
21 funcmem_port = Port("port to functional memory")
22
23class DMASequencer(RubyPort):
24 type = 'DMASequencer'
23
24class DMASequencer(RubyPort):
25 type = 'DMASequencer'