Sequencer.py (13665:9c7fe3811b88) Sequencer.py (13892:0182a0601f66)
1# Copyright (c) 2009 Advanced Micro Devices, Inc.
2# All rights reserved.
3#
4# Redistribution and use in source and binary forms, with or without
5# modification, are permitted provided that the following conditions are
6# met: redistributions of source code must retain the above copyright
7# notice, this list of conditions and the following disclaimer;
8# redistributions in binary form must reproduce the above copyright

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24# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
25# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
26#
27# Authors: Steve Reinhardt
28# Brad Beckmann
29
30from m5.params import *
31from m5.proxy import *
1# Copyright (c) 2009 Advanced Micro Devices, Inc.
2# All rights reserved.
3#
4# Redistribution and use in source and binary forms, with or without
5# modification, are permitted provided that the following conditions are
6# met: redistributions of source code must retain the above copyright
7# notice, this list of conditions and the following disclaimer;
8# redistributions in binary form must reproduce the above copyright

--- 15 unchanged lines hidden (view full) ---

24# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
25# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
26#
27# Authors: Steve Reinhardt
28# Brad Beckmann
29
30from m5.params import *
31from m5.proxy import *
32from m5.objects.MemObject import MemObject
32from m5.objects.ClockedObject import ClockedObject
33
33
34class RubyPort(MemObject):
34class RubyPort(ClockedObject):
35 type = 'RubyPort'
36 abstract = True
37 cxx_header = "mem/ruby/system/RubyPort.hh"
38 version = Param.Int(0, "")
39
40 slave = VectorSlavePort("CPU slave port")
41 master = VectorMasterPort("CPU master port")
42 pio_master_port = MasterPort("Ruby mem master port")

--- 42 unchanged lines hidden --- 		35 type = 'RubyPort'
36 abstract = True
37 cxx_header = "mem/ruby/system/RubyPort.hh"
38 version = Param.Int(0, "")
39
40 slave = VectorSlavePort("CPU slave port")
41 master = VectorMasterPort("CPU master port")
42 pio_master_port = MasterPort("Ruby mem master port")

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