Sequencer.py (10919:80069a602c83) Sequencer.py (11019:fc1e41e88fd3)
1# Copyright (c) 2009 Advanced Micro Devices, Inc.
2# All rights reserved.
3#
4# Redistribution and use in source and binary forms, with or without
5# modification, are permitted provided that the following conditions are
6# met: redistributions of source code must retain the above copyright
7# notice, this list of conditions and the following disclaimer;
8# redistributions in binary form must reproduce the above copyright

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56
57class RubySequencer(RubyPort):
58 type = 'RubySequencer'
59 cxx_class = 'Sequencer'
60 cxx_header = "mem/ruby/system/Sequencer.hh"
61
62 icache = Param.RubyCache("")
63 dcache = Param.RubyCache("")
1# Copyright (c) 2009 Advanced Micro Devices, Inc.
2# All rights reserved.
3#
4# Redistribution and use in source and binary forms, with or without
5# modification, are permitted provided that the following conditions are
6# met: redistributions of source code must retain the above copyright
7# notice, this list of conditions and the following disclaimer;
8# redistributions in binary form must reproduce the above copyright

--- 47 unchanged lines hidden (view full) ---

56
57class RubySequencer(RubyPort):
58 type = 'RubySequencer'
59 cxx_class = 'Sequencer'
60 cxx_header = "mem/ruby/system/Sequencer.hh"
61
62 icache = Param.RubyCache("")
63 dcache = Param.RubyCache("")
64 # Cache latencies currently assessed at the beginning of each access
65 # NOTE: Setting these values to a value greater than one will result in
66 # O3 CPU pipeline bubbles and negatively impact performance
67 # TODO: Latencies should be migrated into each top-level cache controller
68 icache_hit_latency = Param.Cycles(1, "Inst cache hit latency")
69 dcache_hit_latency = Param.Cycles(1, "Data cache hit latency")
64 max_outstanding_requests = Param.Int(16,
65 "max requests (incl. prefetches) outstanding")
66 deadlock_threshold = Param.Cycles(500000,
67 "max outstanding cycles for a request before deadlock/livelock declared")
68 using_network_tester = Param.Bool(False, "")
69
70class DMASequencer(MemObject):
71 type = 'DMASequencer'
72 cxx_header = "mem/ruby/system/DMASequencer.hh"
73
74 version = Param.Int(0, "")
75 slave = SlavePort("Device slave port")
76 using_ruby_tester = Param.Bool(False, "")
77 ruby_system = Param.RubySystem(Parent.any, "")
78 system = Param.System(Parent.any, "system object")
70 max_outstanding_requests = Param.Int(16,
71 "max requests (incl. prefetches) outstanding")
72 deadlock_threshold = Param.Cycles(500000,
73 "max outstanding cycles for a request before deadlock/livelock declared")
74 using_network_tester = Param.Bool(False, "")
75
76class DMASequencer(MemObject):
77 type = 'DMASequencer'
78 cxx_header = "mem/ruby/system/DMASequencer.hh"
79
80 version = Param.Int(0, "")
81 slave = SlavePort("Device slave port")
82 using_ruby_tester = Param.Bool(False, "")
83 ruby_system = Param.RubySystem(Parent.any, "")
84 system = Param.System(Parent.any, "system object")