Sequencer.py (10706:4206946d60fe) Sequencer.py (10919:80069a602c83)
1# Copyright (c) 2009 Advanced Micro Devices, Inc.
2# All rights reserved.
3#
4# Redistribution and use in source and binary forms, with or without
5# modification, are permitted provided that the following conditions are
6# met: redistributions of source code must retain the above copyright
7# notice, this list of conditions and the following disclaimer;
8# redistributions in binary form must reproduce the above copyright

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40 slave = VectorSlavePort("CPU slave port")
41 master = VectorMasterPort("CPU master port")
42 pio_master_port = MasterPort("Ruby mem master port")
43 mem_master_port = MasterPort("Ruby mem master port")
44 pio_slave_port = SlavePort("Ruby pio slave port")
45 mem_slave_port = SlavePort("Ruby memory port")
46
47 using_ruby_tester = Param.Bool(False, "")
1# Copyright (c) 2009 Advanced Micro Devices, Inc.
2# All rights reserved.
3#
4# Redistribution and use in source and binary forms, with or without
5# modification, are permitted provided that the following conditions are
6# met: redistributions of source code must retain the above copyright
7# notice, this list of conditions and the following disclaimer;
8# redistributions in binary form must reproduce the above copyright

--- 31 unchanged lines hidden (view full) ---

40 slave = VectorSlavePort("CPU slave port")
41 master = VectorMasterPort("CPU master port")
42 pio_master_port = MasterPort("Ruby mem master port")
43 mem_master_port = MasterPort("Ruby mem master port")
44 pio_slave_port = SlavePort("Ruby pio slave port")
45 mem_slave_port = SlavePort("Ruby memory port")
46
47 using_ruby_tester = Param.Bool(False, "")
48 ruby_system = Param.RubySystem("")
48 ruby_system = Param.RubySystem(Parent.any, "")
49 system = Param.System(Parent.any, "system object")
50 support_data_reqs = Param.Bool(True, "data cache requests supported")
51 support_inst_reqs = Param.Bool(True, "inst cache requests supported")
52
53class RubyPortProxy(RubyPort):
54 type = 'RubyPortProxy'
55 cxx_header = "mem/ruby/system/RubyPortProxy.hh"
49 system = Param.System(Parent.any, "system object")
50 support_data_reqs = Param.Bool(True, "data cache requests supported")
51 support_inst_reqs = Param.Bool(True, "inst cache requests supported")
52
53class RubyPortProxy(RubyPort):
54 type = 'RubyPortProxy'
55 cxx_header = "mem/ruby/system/RubyPortProxy.hh"
56
56
57class RubySequencer(RubyPort):
58 type = 'RubySequencer'
59 cxx_class = 'Sequencer'
60 cxx_header = "mem/ruby/system/Sequencer.hh"
61
62 icache = Param.RubyCache("")
63 dcache = Param.RubyCache("")
64 max_outstanding_requests = Param.Int(16,

--- 14 unchanged lines hidden --- 		57class RubySequencer(RubyPort):
58 type = 'RubySequencer'
59 cxx_class = 'Sequencer'
60 cxx_header = "mem/ruby/system/Sequencer.hh"
61
62 icache = Param.RubyCache("")
63 dcache = Param.RubyCache("")
64 max_outstanding_requests = Param.Int(16,

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