Sequencer.py (10524:fff17530cef6) Sequencer.py (10525:77787650cbbc)
1# Copyright (c) 2009 Advanced Micro Devices, Inc.
2# All rights reserved.
3#
4# Redistribution and use in source and binary forms, with or without
5# modification, are permitted provided that the following conditions are
6# met: redistributions of source code must retain the above copyright
7# notice, this list of conditions and the following disclaimer;
8# redistributions in binary form must reproduce the above copyright

--- 31 unchanged lines hidden (view full) ---

40 slave = VectorSlavePort("CPU slave port")
41 master = VectorMasterPort("CPU master port")
42 pio_master_port = MasterPort("Ruby mem master port")
43 mem_master_port = MasterPort("Ruby mem master port")
44 pio_slave_port = SlavePort("Ruby pio slave port")
45 mem_slave_port = SlavePort("Ruby memory port")
46
47 using_ruby_tester = Param.Bool(False, "")
1# Copyright (c) 2009 Advanced Micro Devices, Inc.
2# All rights reserved.
3#
4# Redistribution and use in source and binary forms, with or without
5# modification, are permitted provided that the following conditions are
6# met: redistributions of source code must retain the above copyright
7# notice, this list of conditions and the following disclaimer;
8# redistributions in binary form must reproduce the above copyright

--- 31 unchanged lines hidden (view full) ---

40 slave = VectorSlavePort("CPU slave port")
41 master = VectorMasterPort("CPU master port")
42 pio_master_port = MasterPort("Ruby mem master port")
43 mem_master_port = MasterPort("Ruby mem master port")
44 pio_slave_port = SlavePort("Ruby pio slave port")
45 mem_slave_port = SlavePort("Ruby memory port")
46
47 using_ruby_tester = Param.Bool(False, "")
48 access_phys_mem = Param.Bool(False,
48 access_backing_store = Param.Bool(False,
49 "should the rubyport atomically update phys_mem")
50 ruby_system = Param.RubySystem("")
51 system = Param.System(Parent.any, "system object")
52 support_data_reqs = Param.Bool(True, "data cache requests supported")
53 support_inst_reqs = Param.Bool(True, "inst cache requests supported")
54
55class RubyPortProxy(RubyPort):
56 type = 'RubyPortProxy'
57 cxx_header = "mem/ruby/system/RubyPortProxy.hh"
49 "should the rubyport atomically update phys_mem")
50 ruby_system = Param.RubySystem("")
51 system = Param.System(Parent.any, "system object")
52 support_data_reqs = Param.Bool(True, "data cache requests supported")
53 support_inst_reqs = Param.Bool(True, "inst cache requests supported")
54
55class RubyPortProxy(RubyPort):
56 type = 'RubyPortProxy'
57 cxx_header = "mem/ruby/system/RubyPortProxy.hh"
58 access_phys_mem = False
59
60class RubySequencer(RubyPort):
61 type = 'RubySequencer'
62 cxx_class = 'Sequencer'
63 cxx_header = "mem/ruby/system/Sequencer.hh"
64
65 icache = Param.RubyCache("")
66 dcache = Param.RubyCache("")

--- 15 unchanged lines hidden --- 		58
59class RubySequencer(RubyPort):
60 type = 'RubySequencer'
61 cxx_class = 'Sequencer'
62 cxx_header = "mem/ruby/system/Sequencer.hh"
63
64 icache = Param.RubyCache("")
65 dcache = Param.RubyCache("")

--- 15 unchanged lines hidden ---