1# Copyright (c) 2009 Advanced Micro Devices, Inc. 2# All rights reserved. 3# 4# Redistribution and use in source and binary forms, with or without 5# modification, are permitted provided that the following conditions are 6# met: redistributions of source code must retain the above copyright 7# notice, this list of conditions and the following disclaimer; 8# redistributions in binary form must reproduce the above copyright --- 27 unchanged lines hidden (view full) --- 36 abstract = True 37 cxx_header = "mem/ruby/system/RubyPort.hh" 38 slave = VectorSlavePort("CPU slave port") 39 master = VectorMasterPort("CPU master port") 40 version = Param.Int(0, "") 41 pio_port = MasterPort("Ruby_pio_port") 42 using_ruby_tester = Param.Bool(False, "") 43 using_network_tester = Param.Bool(False, "") |
44 access_phys_mem = Param.Bool(False, |
45 "should the rubyport atomically update phys_mem") 46 ruby_system = Param.RubySystem("") 47 system = Param.System(Parent.any, "system object") 48 support_data_reqs = Param.Bool(True, "data cache requests supported") 49 support_inst_reqs = Param.Bool(True, "inst cache requests supported") 50 51 52class RubyPortProxy(RubyPort): 53 type = 'RubyPortProxy' 54 cxx_header = "mem/ruby/system/RubyPortProxy.hh" |
55 access_phys_mem = True |
56 57class RubySequencer(RubyPort): 58 type = 'RubySequencer' 59 cxx_class = 'Sequencer' 60 cxx_header = "mem/ruby/system/Sequencer.hh" 61 icache = Param.RubyCache("") 62 dcache = Param.RubyCache("") 63 max_outstanding_requests = Param.Int(16, 64 "max requests (incl. prefetches) outstanding") 65 deadlock_threshold = Param.Cycles(500000, 66 "max outstanding cycles for a request before deadlock/livelock declared") 67 68class DMASequencer(RubyPort): 69 type = 'DMASequencer' 70 cxx_header = "mem/ruby/system/DMASequencer.hh" |
71 access_phys_mem = True |