1# Copyright (c) 2009 Advanced Micro Devices, Inc. 2# All rights reserved. 3# 4# Redistribution and use in source and binary forms, with or without 5# modification, are permitted provided that the following conditions are 6# met: redistributions of source code must retain the above copyright 7# notice, this list of conditions and the following disclaimer; 8# redistributions in binary form must reproduce the above copyright --- 64 unchanged lines hidden (view full) --- 73 "max requests (incl. prefetches) outstanding") 74 deadlock_threshold = Param.Cycles(500000, 75 "max outstanding cycles for a request before deadlock/livelock declared") 76 using_network_tester = Param.Bool(False, "") 77 # id used by protocols that support multiple sequencers per controller 78 # 99 is the dummy default value 79 coreid = Param.Int(99, "CorePair core id") 80 |
81class DMASequencer(RubyPort): |
82 type = 'DMASequencer' 83 cxx_header = "mem/ruby/system/DMASequencer.hh" |