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<
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< class DMASequencer(RubyPort):
---
> class DMASequencer(MemObject):
77c76,84
< access_phys_mem = True
---
> version = Param.Int(0, "")
>
> slave = SlavePort("Device slave port")
>
> using_ruby_tester = Param.Bool(False, "")
> access_phys_mem = Param.Bool(True,
> "should the dma atomically update phys_mem")
> ruby_system = Param.RubySystem(Parent.any, "")
> system = Param.System(Parent.any, "system object")