1# Copyright (c) 2009 Advanced Micro Devices, Inc.
2# All rights reserved.
3#
4# Redistribution and use in source and binary forms, with or without
5# modification, are permitted provided that the following conditions are
6# met: redistributions of source code must retain the above copyright
7# notice, this list of conditions and the following disclaimer;
8# redistributions in binary form must reproduce the above copyright

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29
30from m5.params import *
31from m5.proxy import *
32from MemObject import MemObject
33
34class RubyPort(MemObject):
35 type = 'RubyPort'
36 abstract = True
37 slave = VectorSlavePort("CPU slave port")
38 master = VectorMasterPort("CPU master port")
39 version = Param.Int(0, "")
40 pio_port = MasterPort("Ruby_pio_port")
41 using_ruby_tester = Param.Bool(False, "")
42 using_network_tester = Param.Bool(False, "")
43 access_phys_mem = Param.Bool(True,
44 "should the rubyport atomically update phys_mem")
45 ruby_system = Param.RubySystem("")
46 system = Param.System(Parent.any, "system object")
47 support_data_reqs = Param.Bool(True, "data cache requests supported")
48 support_inst_reqs = Param.Bool(True, "inst cache requests supported")
49
50
51class RubyPortProxy(RubyPort):
52 type = 'RubyPortProxy'
53
54class RubySequencer(RubyPort):
55 type = 'RubySequencer'
56 cxx_class = 'Sequencer'
57 icache = Param.RubyCache("")
58 dcache = Param.RubyCache("")
59 max_outstanding_requests = Param.Int(16,
60 "max requests (incl. prefetches) outstanding")
61 deadlock_threshold = Param.Cycles(500000,
62 "max outstanding cycles for a request before deadlock/livelock declared")
63
64class DMASequencer(RubyPort):
65 type = 'DMASequencer'