1# Copyright (c) 2009 Advanced Micro Devices, Inc.
2# All rights reserved.
3#
4# Redistribution and use in source and binary forms, with or without
5# modification, are permitted provided that the following conditions are
6# met: redistributions of source code must retain the above copyright
7# notice, this list of conditions and the following disclaimer;
8# redistributions in binary form must reproduce the above copyright

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47 using_ruby_tester = Param.Bool(False, "")
48 access_phys_mem = Param.Bool(False,
49 "should the rubyport atomically update phys_mem")
50 ruby_system = Param.RubySystem("")
51 system = Param.System(Parent.any, "system object")
52 support_data_reqs = Param.Bool(True, "data cache requests supported")
53 support_inst_reqs = Param.Bool(True, "inst cache requests supported")
54
55class RubyPortProxy(RubyPort):
56 type = 'RubyPortProxy'
57 cxx_header = "mem/ruby/system/RubyPortProxy.hh"
58 access_phys_mem = True
59
60class RubySequencer(RubyPort):
61 type = 'RubySequencer'
62 cxx_class = 'Sequencer'
63 cxx_header = "mem/ruby/system/Sequencer.hh"
64
65 icache = Param.RubyCache("")
66 dcache = Param.RubyCache("")
67 max_outstanding_requests = Param.Int(16,
68 "max requests (incl. prefetches) outstanding")
69 deadlock_threshold = Param.Cycles(500000,
70 "max outstanding cycles for a request before deadlock/livelock declared")
71 using_network_tester = Param.Bool(False, "")
72
73class DMASequencer(MemObject):
74 type = 'DMASequencer'
75 cxx_header = "mem/ruby/system/DMASequencer.hh"
76 version = Param.Int(0, "")
77
78 slave = SlavePort("Device slave port")
79
80 using_ruby_tester = Param.Bool(False, "")
81 access_phys_mem = Param.Bool(True,
82 "should the dma atomically update phys_mem")
83 ruby_system = Param.RubySystem(Parent.any, "")
84 system = Param.System(Parent.any, "system object")