Sequencer.hh (9773:915be89faf30) | Sequencer.hh (10012:ec5a5bfb941d) |
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1/* 2 * Copyright (c) 1999-2008 Mark D. Hill and David A. Wood 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; --- 52 unchanged lines hidden (view full) --- 61 public: 62 typedef RubySequencerParams Params; 63 Sequencer(const Params *); 64 ~Sequencer(); 65 66 // Public Methods 67 void wakeup(); // Used only for deadlock detection 68 void printProgress(std::ostream& out) const; | 1/* 2 * Copyright (c) 1999-2008 Mark D. Hill and David A. Wood 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; --- 52 unchanged lines hidden (view full) --- 61 public: 62 typedef RubySequencerParams Params; 63 Sequencer(const Params *); 64 ~Sequencer(); 65 66 // Public Methods 67 void wakeup(); // Used only for deadlock detection 68 void printProgress(std::ostream& out) const; |
69 void clearStats(); | 69 void resetStats(); 70 void collateStats(); 71 void regStats(); |
70 71 void writeCallback(const Address& address, 72 DataBlock& data, 73 const bool externalHit = false, 74 const MachineType mach = MachineType_NUM, 75 const Cycles initialRequestTime = Cycles(0), 76 const Cycles forwardRequestTime = Cycles(0), 77 const Cycles firstResponseTime = Cycles(0)); --- 12 unchanged lines hidden (view full) --- 90 91 bool isDeadlockEventScheduled() const 92 { return deadlockCheckEvent.scheduled(); } 93 94 void descheduleDeadlockEvent() 95 { deschedule(deadlockCheckEvent); } 96 97 void print(std::ostream& out) const; | 72 73 void writeCallback(const Address& address, 74 DataBlock& data, 75 const bool externalHit = false, 76 const MachineType mach = MachineType_NUM, 77 const Cycles initialRequestTime = Cycles(0), 78 const Cycles forwardRequestTime = Cycles(0), 79 const Cycles firstResponseTime = Cycles(0)); --- 12 unchanged lines hidden (view full) --- 92 93 bool isDeadlockEventScheduled() const 94 { return deadlockCheckEvent.scheduled(); } 95 96 void descheduleDeadlockEvent() 97 { deschedule(deadlockCheckEvent); } 98 99 void print(std::ostream& out) const; |
98 void printStats(std::ostream& out) const; | |
99 void checkCoherence(const Address& address); 100 101 void markRemoved(); 102 void removeRequest(SequencerRequest* request); 103 void evictionCallback(const Address& address); 104 void invalidateSC(const Address& address); 105 106 void recordRequestType(SequencerRequestType requestType); | 100 void checkCoherence(const Address& address); 101 102 void markRemoved(); 103 void removeRequest(SequencerRequest* request); 104 void evictionCallback(const Address& address); 105 void invalidateSC(const Address& address); 106 107 void recordRequestType(SequencerRequestType requestType); |
107 Histogram& getOutstandReqHist() { return m_outstandReqHist; } | 108 Stats::Histogram& getOutstandReqHist() { return m_outstandReqHist; } |
108 | 109 |
109 Histogram& getLatencyHist() { return m_latencyHist; } 110 Histogram& getTypeLatencyHist(uint32_t t) 111 { return m_typeLatencyHist[t]; } | 110 Stats::Histogram& getLatencyHist() { return m_latencyHist; } 111 Stats::Histogram& getTypeLatencyHist(uint32_t t) 112 { return *m_typeLatencyHist[t]; } |
112 | 113 |
113 Histogram& getHitLatencyHist() { return m_hitLatencyHist; } 114 Histogram& getHitTypeLatencyHist(uint32_t t) 115 { return m_hitTypeLatencyHist[t]; } | 114 Stats::Histogram& getHitLatencyHist() { return m_hitLatencyHist; } 115 Stats::Histogram& getHitTypeLatencyHist(uint32_t t) 116 { return *m_hitTypeLatencyHist[t]; } |
116 | 117 |
117 Histogram& getHitMachLatencyHist(uint32_t t) 118 { return m_hitMachLatencyHist[t]; } | 118 Stats::Histogram& getHitMachLatencyHist(uint32_t t) 119 { return *m_hitMachLatencyHist[t]; } |
119 | 120 |
120 Histogram& getHitTypeMachLatencyHist(uint32_t r, uint32_t t) 121 { return m_hitTypeMachLatencyHist[r][t]; } | 121 Stats::Histogram& getHitTypeMachLatencyHist(uint32_t r, uint32_t t) 122 { return *m_hitTypeMachLatencyHist[r][t]; } |
122 | 123 |
123 Histogram& getMissLatencyHist() { return m_missLatencyHist; } 124 Histogram& getMissTypeLatencyHist(uint32_t t) 125 { return m_missTypeLatencyHist[t]; } | 124 Stats::Histogram& getMissLatencyHist() 125 { return m_missLatencyHist; } 126 Stats::Histogram& getMissTypeLatencyHist(uint32_t t) 127 { return *m_missTypeLatencyHist[t]; } |
126 | 128 |
127 Histogram& getMissMachLatencyHist(uint32_t t) 128 { return m_missMachLatencyHist[t]; } | 129 Stats::Histogram& getMissMachLatencyHist(uint32_t t) const 130 { return *m_missMachLatencyHist[t]; } |
129 | 131 |
130 Histogram& getMissTypeMachLatencyHist(uint32_t r, uint32_t t) 131 { return m_missTypeMachLatencyHist[r][t]; } | 132 Stats::Histogram& 133 getMissTypeMachLatencyHist(uint32_t r, uint32_t t) const 134 { return *m_missTypeMachLatencyHist[r][t]; } |
132 | 135 |
133 Histogram& getIssueToInitialDelayHist(uint32_t t) 134 { return m_IssueToInitialDelayHist[t]; } | 136 Stats::Histogram& getIssueToInitialDelayHist(uint32_t t) const 137 { return *m_IssueToInitialDelayHist[t]; } |
135 | 138 |
136 Histogram& getInitialToForwardDelayHist(const MachineType t) 137 { return m_InitialToForwardDelayHist[t]; } | 139 Stats::Histogram& 140 getInitialToForwardDelayHist(const MachineType t) const 141 { return *m_InitialToForwardDelayHist[t]; } |
138 | 142 |
139 Histogram& getForwardRequestToFirstResponseHist(const MachineType t) 140 { return m_ForwardToFirstResponseDelayHist[t]; } | 143 Stats::Histogram& 144 getForwardRequestToFirstResponseHist(const MachineType t) const 145 { return *m_ForwardToFirstResponseDelayHist[t]; } |
141 | 146 |
142 Histogram& getFirstResponseToCompletionDelayHist(const MachineType t) 143 { return m_FirstResponseToCompletionDelayHist[t]; } | 147 Stats::Histogram& 148 getFirstResponseToCompletionDelayHist(const MachineType t) const 149 { return *m_FirstResponseToCompletionDelayHist[t]; } |
144 | 150 |
145 const uint64_t getIncompleteTimes(const MachineType t) const | 151 Stats::Counter getIncompleteTimes(const MachineType t) const |
146 { return m_IncompleteTimes[t]; } 147 148 private: 149 void issueRequest(PacketPtr pkt, RubyRequestType type); 150 151 void hitCallback(SequencerRequest* request, DataBlock& data, 152 bool llscSuccess, 153 const MachineType mach, const bool externalHit, --- 24 unchanged lines hidden (view full) --- 178 179 typedef m5::hash_map<Address, SequencerRequest*> RequestTable; 180 RequestTable m_writeRequestTable; 181 RequestTable m_readRequestTable; 182 // Global outstanding request count, across all request tables 183 int m_outstanding_count; 184 bool m_deadlock_check_scheduled; 185 | 152 { return m_IncompleteTimes[t]; } 153 154 private: 155 void issueRequest(PacketPtr pkt, RubyRequestType type); 156 157 void hitCallback(SequencerRequest* request, DataBlock& data, 158 bool llscSuccess, 159 const MachineType mach, const bool externalHit, --- 24 unchanged lines hidden (view full) --- 184 185 typedef m5::hash_map<Address, SequencerRequest*> RequestTable; 186 RequestTable m_writeRequestTable; 187 RequestTable m_readRequestTable; 188 // Global outstanding request count, across all request tables 189 int m_outstanding_count; 190 bool m_deadlock_check_scheduled; 191 |
186 uint32_t m_store_waiting_on_load_cycles; 187 uint32_t m_store_waiting_on_store_cycles; 188 uint32_t m_load_waiting_on_store_cycles; 189 uint32_t m_load_waiting_on_load_cycles; | 192 //! Counters for recording aliasing information. 193 Stats::Scalar m_store_waiting_on_load; 194 Stats::Scalar m_store_waiting_on_store; 195 Stats::Scalar m_load_waiting_on_store; 196 Stats::Scalar m_load_waiting_on_load; |
190 191 bool m_usingNetworkTester; 192 193 //! Histogram for number of outstanding requests per cycle. | 197 198 bool m_usingNetworkTester; 199 200 //! Histogram for number of outstanding requests per cycle. |
194 Histogram m_outstandReqHist; | 201 Stats::Histogram m_outstandReqHist; |
195 196 //! Histogram for holding latency profile of all requests. | 202 203 //! Histogram for holding latency profile of all requests. |
197 Histogram m_latencyHist; 198 std::vector<Histogram> m_typeLatencyHist; | 204 Stats::Histogram m_latencyHist; 205 std::vector<Stats::Histogram *> m_typeLatencyHist; |
199 200 //! Histogram for holding latency profile of all requests that 201 //! hit in the controller connected to this sequencer. | 206 207 //! Histogram for holding latency profile of all requests that 208 //! hit in the controller connected to this sequencer. |
202 Histogram m_hitLatencyHist; 203 std::vector<Histogram> m_hitTypeLatencyHist; | 209 Stats::Histogram m_hitLatencyHist; 210 std::vector<Stats::Histogram *> m_hitTypeLatencyHist; |
204 205 //! Histograms for profiling the latencies for requests that 206 //! did not required external messages. | 211 212 //! Histograms for profiling the latencies for requests that 213 //! did not required external messages. |
207 std::vector<Histogram> m_hitMachLatencyHist; 208 std::vector< std::vector<Histogram> > m_hitTypeMachLatencyHist; | 214 std::vector<Stats::Histogram *> m_hitMachLatencyHist; 215 std::vector< std::vector<Stats::Histogram *> > m_hitTypeMachLatencyHist; |
209 210 //! Histogram for holding latency profile of all requests that 211 //! miss in the controller connected to this sequencer. | 216 217 //! Histogram for holding latency profile of all requests that 218 //! miss in the controller connected to this sequencer. |
212 Histogram m_missLatencyHist; 213 std::vector<Histogram> m_missTypeLatencyHist; | 219 Stats::Histogram m_missLatencyHist; 220 std::vector<Stats::Histogram *> m_missTypeLatencyHist; |
214 215 //! Histograms for profiling the latencies for requests that 216 //! required external messages. | 221 222 //! Histograms for profiling the latencies for requests that 223 //! required external messages. |
217 std::vector<Histogram> m_missMachLatencyHist; 218 std::vector< std::vector<Histogram> > m_missTypeMachLatencyHist; | 224 std::vector<Stats::Histogram *> m_missMachLatencyHist; 225 std::vector< std::vector<Stats::Histogram *> > m_missTypeMachLatencyHist; |
219 220 //! Histograms for recording the breakdown of miss latency | 226 227 //! Histograms for recording the breakdown of miss latency |
221 std::vector<Histogram> m_IssueToInitialDelayHist; 222 std::vector<Histogram> m_InitialToForwardDelayHist; 223 std::vector<Histogram> m_ForwardToFirstResponseDelayHist; 224 std::vector<Histogram> m_FirstResponseToCompletionDelayHist; 225 std::vector<uint64_t> m_IncompleteTimes; | 228 std::vector<Stats::Histogram *> m_IssueToInitialDelayHist; 229 std::vector<Stats::Histogram *> m_InitialToForwardDelayHist; 230 std::vector<Stats::Histogram *> m_ForwardToFirstResponseDelayHist; 231 std::vector<Stats::Histogram *> m_FirstResponseToCompletionDelayHist; 232 std::vector<Stats::Counter> m_IncompleteTimes; |
226 227 228 class SequencerWakeupEvent : public Event 229 { 230 private: 231 Sequencer *m_sequencer_ptr; 232 233 public: --- 17 unchanged lines hidden --- | 233 234 235 class SequencerWakeupEvent : public Event 236 { 237 private: 238 Sequencer *m_sequencer_ptr; 239 240 public: --- 17 unchanged lines hidden --- |