Sequencer.hh (6876:a658c315512c) Sequencer.hh (6882:898047a3672c)
1
2/*
3 * Copyright (c) 1999-2008 Mark D. Hill and David A. Wood
4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are
8 * met: redistributions of source code must retain the above copyright

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113
114private:
115 int m_max_outstanding_requests;
116 int m_deadlock_threshold;
117
118 CacheMemory* m_dataCache_ptr;
119 CacheMemory* m_instCache_ptr;
120
1
2/*
3 * Copyright (c) 1999-2008 Mark D. Hill and David A. Wood
4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are
8 * met: redistributions of source code must retain the above copyright

--- 104 unchanged lines hidden (view full) ---

113
114private:
115 int m_max_outstanding_requests;
116 int m_deadlock_threshold;
117
118 CacheMemory* m_dataCache_ptr;
119 CacheMemory* m_instCache_ptr;
120
121 // indicates what processor on the chip this sequencer is associated with
122 int m_controller_type;
123
124 Map<Address, SequencerRequest*> m_writeRequestTable;
125 Map<Address, SequencerRequest*> m_readRequestTable;
126 // Global outstanding request count, across all request tables
127 int m_outstanding_count;
128 bool m_deadlock_check_scheduled;
129
130 int m_store_waiting_on_load_cycles;
131 int m_store_waiting_on_store_cycles;

--- 20 unchanged lines hidden --- 		121 Map<Address, SequencerRequest*> m_writeRequestTable;
122 Map<Address, SequencerRequest*> m_readRequestTable;
123 // Global outstanding request count, across all request tables
124 int m_outstanding_count;
125 bool m_deadlock_check_scheduled;
126
127 int m_store_waiting_on_load_cycles;
128 int m_store_waiting_on_store_cycles;

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