Sequencer.hh (6284:a63d1dc4c820) Sequencer.hh (6285:ce086eca1ede)
1
2/*
3 * Copyright (c) 1999-2008 Mark D. Hill and David A. Wood
4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are
8 * met: redistributions of source code must retain the above copyright

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39
40#include "mem/ruby/common/Global.hh"
41#include "mem/ruby/config/RubyConfig.hh"
42#include "mem/ruby/common/Consumer.hh"
43#include "mem/protocol/CacheRequestType.hh"
44#include "mem/protocol/AccessModeType.hh"
45#include "mem/protocol/GenericMachineType.hh"
46#include "mem/protocol/PrefetchBit.hh"
1
2/*
3 * Copyright (c) 1999-2008 Mark D. Hill and David A. Wood
4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are
8 * met: redistributions of source code must retain the above copyright

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39
40#include "mem/ruby/common/Global.hh"
41#include "mem/ruby/config/RubyConfig.hh"
42#include "mem/ruby/common/Consumer.hh"
43#include "mem/protocol/CacheRequestType.hh"
44#include "mem/protocol/AccessModeType.hh"
45#include "mem/protocol/GenericMachineType.hh"
46#include "mem/protocol/PrefetchBit.hh"
47#include "mem/ruby/system/RubyPort.hh"
47#include "mem/gems_common/Map.hh"
48#include "mem/gems_common/Map.hh"
49#include "mem/ruby/common/Address.hh"
48
49class DataBlock;
50
51class DataBlock;
50class AbstractChip;
51class CacheMsg;
52class CacheMsg;
52class Address;
53class MachineID;
53class MachineID;
54class Packet;
54class CacheMemory;
55class AbstractController;
55
56
56class Sequencer : public Consumer {
57struct SequencerRequest {
58 RubyRequest ruby_request;
59 int64_t id;
60 Time issue_time;
61
62 SequencerRequest(const RubyRequest & _ruby_request, int64_t _id, Time _issue_time)
63 : ruby_request(_ruby_request), id(_id), issue_time(_issue_time)
64 {}
65};
66
67class Sequencer : public Consumer, public RubyPort {
57public:
58 // Constructors
68public:
69 // Constructors
59 Sequencer(AbstractChip* chip_ptr, int version);
70 Sequencer(const string & name);
71 void init(const vector<string> & argv);
60
61 // Destructor
62 ~Sequencer();
63
64 // Public Methods
65 void wakeup(); // Used only for deadlock detection
66
72
73 // Destructor
74 ~Sequencer();
75
76 // Public Methods
77 void wakeup(); // Used only for deadlock detection
78
67 static void printConfig(ostream& out);
79 void printConfig(ostream& out) const;
68
80
69 // returns total number of outstanding request (includes prefetches)
70 int getNumberOutstanding();
71 // return only total number of outstanding demand requests
72 int getNumberOutstandingDemand();
73 // return only total number of outstanding prefetch requests
74 int getNumberOutstandingPrefetch();
75
76 // remove load/store request from queue
77 void removeLoadRequest(const Address & addr, int thread);
78 void removeStoreRequest(const Address & addr, int thread);
79
80 void printProgress(ostream& out) const;
81
81 void printProgress(ostream& out) const;
82
82 // returns a pointer to the request in the request tables
83 CacheMsg & getReadRequest( const Address & addr, int thread );
84 CacheMsg & getWriteRequest( const Address & addr, int thread );
85
86 void writeCallback(const Address& address, DataBlock& data);
87 void readCallback(const Address& address, DataBlock& data);
83 void writeCallback(const Address& address, DataBlock& data);
84 void readCallback(const Address& address, DataBlock& data);
88 void writeCallback(const Address& address);
89 void readCallback(const Address& address);
90 void writeCallback(const Address& address, DataBlock& data, GenericMachineType respondingMach, PrefetchBit pf, int thread);
91 void readCallback(const Address& address, DataBlock& data, GenericMachineType respondingMach, PrefetchBit pf, int thread);
92 void writeCallback(const Address& address, DataBlock& data, GenericMachineType respondingMach, int thread);
93 void readCallback(const Address& address, DataBlock& data, GenericMachineType respondingMach, int thread);
94
85
95 // returns the thread ID of the request
96 int getRequestThreadID(const Address & addr);
97 // returns the physical address of the request
98 Address getRequestPhysicalAddress(const Address & lineaddr);
99 // returns whether a request is a prefetch request
100 bool isPrefetchRequest(const Address & lineaddr);
101
102 //notifies driver of debug print
103 void printDebug();
104
105 // called by Tester or Simics
86 // called by Tester or Simics
106 void makeRequest(Packet* pkt);
107 bool doRequest(const CacheMsg& request);
108 void issueRequest(const CacheMsg& request);
109 bool isReady(const Packet* pkt) const;
110 bool isReady(const CacheMsg& request) const; // depricate this function
87 int64_t makeRequest(const RubyRequest & request);
88 bool isReady(const RubyRequest& request) const;
111 bool empty() const;
89 bool empty() const;
112 void resetRequestTime(const Address& addr, int thread);
113 Address getLogicalAddressOfRequest(Address address, int thread);
114 AccessModeType getAccessModeOfRequest(Address address, int thread);
115 //uint64 getSequenceNumberOfRequest(Address addr, int thread);
116
117 void print(ostream& out) const;
118 void checkCoherence(const Address& address);
119
90
91 void print(ostream& out) const;
92 void checkCoherence(const Address& address);
93
120 bool getRubyMemoryValue(const Address& addr, char* value, unsigned int size_in_bytes);
121 bool setRubyMemoryValue(const Address& addr, char *value, unsigned int size_in_bytes);
94 // bool getRubyMemoryValue(const Address& addr, char* value, unsigned int size_in_bytes);
95 // bool setRubyMemoryValue(const Address& addr, char *value, unsigned int size_in_bytes);
122
96
123 void removeRequest(const CacheMsg& request);
97 void removeRequest(SequencerRequest* request);
124private:
125 // Private Methods
126 bool tryCacheAccess(const Address& addr, CacheRequestType type, const Address& pc, AccessModeType access_mode, int size, DataBlock*& data_ptr);
98private:
99 // Private Methods
100 bool tryCacheAccess(const Address& addr, CacheRequestType type, const Address& pc, AccessModeType access_mode, int size, DataBlock*& data_ptr);
127 // void conflictCallback(const CacheMsg& request, GenericMachineType respondingMach, int thread);
128 void hitCallback(const CacheMsg& request, DataBlock& data, GenericMachineType respondingMach, int thread);
129 bool insertRequest(const CacheMsg& request);
101 void issueRequest(const RubyRequest& request);
130
102
103 void hitCallback(SequencerRequest* request, DataBlock& data);
104 bool insertRequest(SequencerRequest* request);
131
105
106
132 // Private copy constructor and assignment operator
133 Sequencer(const Sequencer& obj);
134 Sequencer& operator=(const Sequencer& obj);
135
107 // Private copy constructor and assignment operator
108 Sequencer(const Sequencer& obj);
109 Sequencer& operator=(const Sequencer& obj);
110
136 // Data Members (m_ prefix)
137 AbstractChip* m_chip_ptr;
111private:
112 int m_max_outstanding_requests;
113 int m_deadlock_threshold;
138
114
115 AbstractController* m_controller;
116 MessageBuffer* m_mandatory_q_ptr;
117 CacheMemory* m_dataCache_ptr;
118 CacheMemory* m_instCache_ptr;
119
139 // indicates what processor on the chip this sequencer is associated with
140 int m_version;
120 // indicates what processor on the chip this sequencer is associated with
121 int m_version;
122 int m_controller_type;
141
123
142 // One request table per SMT thread
143 Map<Address, CacheMsg>** m_writeRequestTable_ptr;
144 Map<Address, CacheMsg>** m_readRequestTable_ptr;
145
146 Map<Address, Packet*>* m_packetTable_ptr;
147
124 Map<Address, SequencerRequest*> m_writeRequestTable;
125 Map<Address, SequencerRequest*> m_readRequestTable;
148 // Global outstanding request count, across all request tables
149 int m_outstanding_count;
150 bool m_deadlock_check_scheduled;
151
152};
153
154// Output operator declaration
155ostream& operator<<(ostream& out, const Sequencer& obj);

--- 14 unchanged lines hidden --- 		126 // Global outstanding request count, across all request tables
127 int m_outstanding_count;
128 bool m_deadlock_check_scheduled;
129
130};
131
132// Output operator declaration
133ostream& operator<<(ostream& out, const Sequencer& obj);

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