Sequencer.hh (6162:cbd6debc4fd0) Sequencer.hh (6165:2d26c346f1be)
1
2/*
3 * Copyright (c) 1999-2008 Mark D. Hill and David A. Wood
4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are
8 * met: redistributions of source code must retain the above copyright

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40#include "mem/ruby/common/Global.hh"
41#include "mem/ruby/config/RubyConfig.hh"
42#include "mem/ruby/common/Consumer.hh"
43#include "mem/protocol/CacheRequestType.hh"
44#include "mem/protocol/AccessModeType.hh"
45#include "mem/protocol/GenericMachineType.hh"
46#include "mem/protocol/PrefetchBit.hh"
47#include "mem/gems_common/Map.hh"
1
2/*
3 * Copyright (c) 1999-2008 Mark D. Hill and David A. Wood
4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are
8 * met: redistributions of source code must retain the above copyright

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40#include "mem/ruby/common/Global.hh"
41#include "mem/ruby/config/RubyConfig.hh"
42#include "mem/ruby/common/Consumer.hh"
43#include "mem/protocol/CacheRequestType.hh"
44#include "mem/protocol/AccessModeType.hh"
45#include "mem/protocol/GenericMachineType.hh"
46#include "mem/protocol/PrefetchBit.hh"
47#include "mem/gems_common/Map.hh"
48#include "mem/packet.hh"
49
50class DataBlock;
51class AbstractChip;
52class CacheMsg;
53class Address;
54class MachineID;
48
49class DataBlock;
50class AbstractChip;
51class CacheMsg;
52class Address;
53class MachineID;
54class Packet;
55
56class Sequencer : public Consumer {
57public:
58 // Constructors
59 Sequencer(AbstractChip* chip_ptr, int version);
60
61 // Destructor
62 ~Sequencer();

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98 Address getRequestPhysicalAddress(const Address & lineaddr);
99 // returns whether a request is a prefetch request
100 bool isPrefetchRequest(const Address & lineaddr);
101
102 //notifies driver of debug print
103 void printDebug();
104
105 // called by Tester or Simics
55
56class Sequencer : public Consumer {
57public:
58 // Constructors
59 Sequencer(AbstractChip* chip_ptr, int version);
60
61 // Destructor
62 ~Sequencer();

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98 Address getRequestPhysicalAddress(const Address & lineaddr);
99 // returns whether a request is a prefetch request
100 bool isPrefetchRequest(const Address & lineaddr);
101
102 //notifies driver of debug print
103 void printDebug();
104
105 // called by Tester or Simics
106 void makeRequest(const Packet* pkt, void* data);
107 void makeRequest(const CacheMsg& request); // depricate this function
106 void makeRequest(Packet* pkt);
108 bool doRequest(const CacheMsg& request);
109 void issueRequest(const CacheMsg& request);
110 bool isReady(const Packet* pkt) const;
111 bool isReady(const CacheMsg& request) const; // depricate this function
112 bool empty() const;
113 void resetRequestTime(const Address& addr, int thread);
114 Address getLogicalAddressOfRequest(Address address, int thread);
115 AccessModeType getAccessModeOfRequest(Address address, int thread);

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138 AbstractChip* m_chip_ptr;
139
140 // indicates what processor on the chip this sequencer is associated with
141 int m_version;
142
143 // One request table per SMT thread
144 Map<Address, CacheMsg>** m_writeRequestTable_ptr;
145 Map<Address, CacheMsg>** m_readRequestTable_ptr;
107 bool doRequest(const CacheMsg& request);
108 void issueRequest(const CacheMsg& request);
109 bool isReady(const Packet* pkt) const;
110 bool isReady(const CacheMsg& request) const; // depricate this function
111 bool empty() const;
112 void resetRequestTime(const Address& addr, int thread);
113 Address getLogicalAddressOfRequest(Address address, int thread);
114 AccessModeType getAccessModeOfRequest(Address address, int thread);

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137 AbstractChip* m_chip_ptr;
138
139 // indicates what processor on the chip this sequencer is associated with
140 int m_version;
141
142 // One request table per SMT thread
143 Map<Address, CacheMsg>** m_writeRequestTable_ptr;
144 Map<Address, CacheMsg>** m_readRequestTable_ptr;
145
146 Map<Address, Packet*>* m_packetTable_ptr;
147
146 // Global outstanding request count, across all request tables
147 int m_outstanding_count;
148 bool m_deadlock_check_scheduled;
149
150};
151
152// Output operator declaration
153ostream& operator<<(ostream& out, const Sequencer& obj);

--- 14 unchanged lines hidden --- 		148 // Global outstanding request count, across all request tables
149 int m_outstanding_count;
150 bool m_deadlock_check_scheduled;
151
152};
153
154// Output operator declaration
155ostream& operator<<(ostream& out, const Sequencer& obj);

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