Sequencer.hh (11110:8647458d421d) Sequencer.hh (11168:f98eb2da15a4)
1/*
2 * Copyright (c) 1999-2008 Mark D. Hill and David A. Wood
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

--- 16 unchanged lines hidden (view full) ---

25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
29#ifndef __MEM_RUBY_SYSTEM_SEQUENCER_HH__
30#define __MEM_RUBY_SYSTEM_SEQUENCER_HH__
31
32#include <iostream>
1/*
2 * Copyright (c) 1999-2008 Mark D. Hill and David A. Wood
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

--- 16 unchanged lines hidden (view full) ---

25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
29#ifndef __MEM_RUBY_SYSTEM_SEQUENCER_HH__
30#define __MEM_RUBY_SYSTEM_SEQUENCER_HH__
31
32#include <iostream>
33#include <unordered_map>
33
34
34#include "base/hashmap.hh"
35#include "mem/protocol/MachineType.hh"
36#include "mem/protocol/RubyRequestType.hh"
37#include "mem/protocol/SequencerRequestType.hh"
38#include "mem/ruby/common/Address.hh"
39#include "mem/ruby/structures/CacheMemory.hh"
40#include "mem/ruby/system/RubyPort.hh"
41#include "params/RubySequencer.hh"
42

--- 137 unchanged lines hidden (view full) ---

180
181 // The cache access latency for top-level caches (L0/L1). These are
182 // currently assessed at the beginning of each memory access through the
183 // sequencer.
184 // TODO: Migrate these latencies into top-level cache controllers.
185 Cycles m_data_cache_hit_latency;
186 Cycles m_inst_cache_hit_latency;
187
35#include "mem/protocol/MachineType.hh"
36#include "mem/protocol/RubyRequestType.hh"
37#include "mem/protocol/SequencerRequestType.hh"
38#include "mem/ruby/common/Address.hh"
39#include "mem/ruby/structures/CacheMemory.hh"
40#include "mem/ruby/system/RubyPort.hh"
41#include "params/RubySequencer.hh"
42

--- 137 unchanged lines hidden (view full) ---

180
181 // The cache access latency for top-level caches (L0/L1). These are
182 // currently assessed at the beginning of each memory access through the
183 // sequencer.
184 // TODO: Migrate these latencies into top-level cache controllers.
185 Cycles m_data_cache_hit_latency;
186 Cycles m_inst_cache_hit_latency;
187
188 typedef m5::hash_map<Addr, SequencerRequest*> RequestTable;
188 typedef std::unordered_map<Addr, SequencerRequest*> RequestTable;
189 RequestTable m_writeRequestTable;
190 RequestTable m_readRequestTable;
191 // Global outstanding request count, across all request tables
192 int m_outstanding_count;
193 bool m_deadlock_check_scheduled;
194
195 //! Counters for recording aliasing information.
196 Stats::Scalar m_store_waiting_on_load;

--- 64 unchanged lines hidden --- 		189 RequestTable m_writeRequestTable;
190 RequestTable m_readRequestTable;
191 // Global outstanding request count, across all request tables
192 int m_outstanding_count;
193 bool m_deadlock_check_scheduled;
194
195 //! Counters for recording aliasing information.
196 Stats::Scalar m_store_waiting_on_load;

--- 64 unchanged lines hidden ---