1/* 2 * Copyright (c) 1999-2008 Mark D. Hill and David A. Wood 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; 9 * redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution; 12 * neither the name of the copyright holders nor the names of its 13 * contributors may be used to endorse or promote products derived from 14 * this software without specific prior written permission. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29#ifndef __MEM_RUBY_SYSTEM_SEQUENCER_HH__ 30#define __MEM_RUBY_SYSTEM_SEQUENCER_HH__ 31 32#include <iostream> 33 34#include "base/hashmap.hh" 35#include "mem/protocol/MachineType.hh" 36#include "mem/protocol/RubyRequestType.hh" 37#include "mem/protocol/SequencerRequestType.hh" 38#include "mem/ruby/common/Address.hh" 39#include "mem/ruby/system/CacheMemory.hh" 40#include "mem/ruby/system/RubyPort.hh" 41#include "params/RubySequencer.hh" 42 43class DataBlock; 44 45struct SequencerRequest 46{ 47 PacketPtr pkt; 48 RubyRequestType m_type; 49 Cycles issue_time; 50 51 SequencerRequest(PacketPtr _pkt, RubyRequestType _m_type, 52 Cycles _issue_time) 53 : pkt(_pkt), m_type(_m_type), issue_time(_issue_time) 54 {} 55}; 56 57std::ostream& operator<<(std::ostream& out, const SequencerRequest& obj); 58 59class Sequencer : public RubyPort 60{ 61 public: 62 typedef RubySequencerParams Params; 63 Sequencer(const Params *); 64 ~Sequencer(); 65 66 // Public Methods 67 void wakeup(); // Used only for deadlock detection 68 void printProgress(std::ostream& out) const;
|
69 void clearStats();
|
69 void resetStats(); 70 void collateStats(); 71 void regStats(); |
72 73 void writeCallback(const Address& address, 74 DataBlock& data, 75 const bool externalHit = false, 76 const MachineType mach = MachineType_NUM, 77 const Cycles initialRequestTime = Cycles(0), 78 const Cycles forwardRequestTime = Cycles(0), 79 const Cycles firstResponseTime = Cycles(0)); 80 81 void readCallback(const Address& address, 82 DataBlock& data, 83 const bool externalHit = false, 84 const MachineType mach = MachineType_NUM, 85 const Cycles initialRequestTime = Cycles(0), 86 const Cycles forwardRequestTime = Cycles(0), 87 const Cycles firstResponseTime = Cycles(0)); 88 89 RequestStatus makeRequest(PacketPtr pkt); 90 bool empty() const; 91 int outstandingCount() const { return m_outstanding_count; } 92 93 bool isDeadlockEventScheduled() const 94 { return deadlockCheckEvent.scheduled(); } 95 96 void descheduleDeadlockEvent() 97 { deschedule(deadlockCheckEvent); } 98 99 void print(std::ostream& out) const;
|
98 void printStats(std::ostream& out) const;
|
100 void checkCoherence(const Address& address); 101 102 void markRemoved(); 103 void removeRequest(SequencerRequest* request); 104 void evictionCallback(const Address& address); 105 void invalidateSC(const Address& address); 106 107 void recordRequestType(SequencerRequestType requestType);
|
107 Histogram& getOutstandReqHist() { return m_outstandReqHist; }
|
108 Stats::Histogram& getOutstandReqHist() { return m_outstandReqHist; } |
109
|
109 Histogram& getLatencyHist() { return m_latencyHist; }
110 Histogram& getTypeLatencyHist(uint32_t t)
111 { return m_typeLatencyHist[t]; }
|
110 Stats::Histogram& getLatencyHist() { return m_latencyHist; } 111 Stats::Histogram& getTypeLatencyHist(uint32_t t) 112 { return *m_typeLatencyHist[t]; } |
113
|
113 Histogram& getHitLatencyHist() { return m_hitLatencyHist; }
114 Histogram& getHitTypeLatencyHist(uint32_t t)
115 { return m_hitTypeLatencyHist[t]; }
|
114 Stats::Histogram& getHitLatencyHist() { return m_hitLatencyHist; } 115 Stats::Histogram& getHitTypeLatencyHist(uint32_t t) 116 { return *m_hitTypeLatencyHist[t]; } |
117
|
117 Histogram& getHitMachLatencyHist(uint32_t t)
118 { return m_hitMachLatencyHist[t]; }
|
118 Stats::Histogram& getHitMachLatencyHist(uint32_t t) 119 { return *m_hitMachLatencyHist[t]; } |
120
|
120 Histogram& getHitTypeMachLatencyHist(uint32_t r, uint32_t t)
121 { return m_hitTypeMachLatencyHist[r][t]; }
|
121 Stats::Histogram& getHitTypeMachLatencyHist(uint32_t r, uint32_t t) 122 { return *m_hitTypeMachLatencyHist[r][t]; } |
123
|
123 Histogram& getMissLatencyHist() { return m_missLatencyHist; }
124 Histogram& getMissTypeLatencyHist(uint32_t t)
125 { return m_missTypeLatencyHist[t]; }
|
124 Stats::Histogram& getMissLatencyHist() 125 { return m_missLatencyHist; } 126 Stats::Histogram& getMissTypeLatencyHist(uint32_t t) 127 { return *m_missTypeLatencyHist[t]; } |
128
|
127 Histogram& getMissMachLatencyHist(uint32_t t)
128 { return m_missMachLatencyHist[t]; }
|
129 Stats::Histogram& getMissMachLatencyHist(uint32_t t) const 130 { return *m_missMachLatencyHist[t]; } |
131
|
130 Histogram& getMissTypeMachLatencyHist(uint32_t r, uint32_t t)
131 { return m_missTypeMachLatencyHist[r][t]; }
|
132 Stats::Histogram& 133 getMissTypeMachLatencyHist(uint32_t r, uint32_t t) const 134 { return *m_missTypeMachLatencyHist[r][t]; } |
135
|
133 Histogram& getIssueToInitialDelayHist(uint32_t t)
134 { return m_IssueToInitialDelayHist[t]; }
|
136 Stats::Histogram& getIssueToInitialDelayHist(uint32_t t) const 137 { return *m_IssueToInitialDelayHist[t]; } |
138
|
136 Histogram& getInitialToForwardDelayHist(const MachineType t)
137 { return m_InitialToForwardDelayHist[t]; }
|
139 Stats::Histogram& 140 getInitialToForwardDelayHist(const MachineType t) const 141 { return *m_InitialToForwardDelayHist[t]; } |
142
|
139 Histogram& getForwardRequestToFirstResponseHist(const MachineType t)
140 { return m_ForwardToFirstResponseDelayHist[t]; }
|
143 Stats::Histogram& 144 getForwardRequestToFirstResponseHist(const MachineType t) const 145 { return *m_ForwardToFirstResponseDelayHist[t]; } |
146
|
142 Histogram& getFirstResponseToCompletionDelayHist(const MachineType t)
143 { return m_FirstResponseToCompletionDelayHist[t]; }
|
147 Stats::Histogram& 148 getFirstResponseToCompletionDelayHist(const MachineType t) const 149 { return *m_FirstResponseToCompletionDelayHist[t]; } |
150
|
145 const uint64_t getIncompleteTimes(const MachineType t) const
|
151 Stats::Counter getIncompleteTimes(const MachineType t) const |
152 { return m_IncompleteTimes[t]; } 153 154 private: 155 void issueRequest(PacketPtr pkt, RubyRequestType type); 156 157 void hitCallback(SequencerRequest* request, DataBlock& data, 158 bool llscSuccess, 159 const MachineType mach, const bool externalHit, 160 const Cycles initialRequestTime, 161 const Cycles forwardRequestTime, 162 const Cycles firstResponseTime); 163 164 void recordMissLatency(const Cycles t, const RubyRequestType type, 165 const MachineType respondingMach, 166 bool isExternalHit, Cycles issuedTime, 167 Cycles initialRequestTime, 168 Cycles forwardRequestTime, Cycles firstResponseTime, 169 Cycles completionTime); 170 171 RequestStatus insertRequest(PacketPtr pkt, RubyRequestType request_type); 172 bool handleLlsc(const Address& address, SequencerRequest* request); 173 174 // Private copy constructor and assignment operator 175 Sequencer(const Sequencer& obj); 176 Sequencer& operator=(const Sequencer& obj); 177 178 private: 179 int m_max_outstanding_requests; 180 Cycles m_deadlock_threshold; 181 182 CacheMemory* m_dataCache_ptr; 183 CacheMemory* m_instCache_ptr; 184 185 typedef m5::hash_map<Address, SequencerRequest*> RequestTable; 186 RequestTable m_writeRequestTable; 187 RequestTable m_readRequestTable; 188 // Global outstanding request count, across all request tables 189 int m_outstanding_count; 190 bool m_deadlock_check_scheduled; 191
|
186 uint32_t m_store_waiting_on_load_cycles;
187 uint32_t m_store_waiting_on_store_cycles;
188 uint32_t m_load_waiting_on_store_cycles;
189 uint32_t m_load_waiting_on_load_cycles;
|
192 //! Counters for recording aliasing information. 193 Stats::Scalar m_store_waiting_on_load; 194 Stats::Scalar m_store_waiting_on_store; 195 Stats::Scalar m_load_waiting_on_store; 196 Stats::Scalar m_load_waiting_on_load; |
197 198 bool m_usingNetworkTester; 199 200 //! Histogram for number of outstanding requests per cycle.
|
194 Histogram m_outstandReqHist;
|
201 Stats::Histogram m_outstandReqHist; |
202 203 //! Histogram for holding latency profile of all requests.
|
197 Histogram m_latencyHist;
198 std::vector<Histogram> m_typeLatencyHist;
|
204 Stats::Histogram m_latencyHist; 205 std::vector<Stats::Histogram *> m_typeLatencyHist; |
206 207 //! Histogram for holding latency profile of all requests that 208 //! hit in the controller connected to this sequencer.
|
202 Histogram m_hitLatencyHist;
203 std::vector<Histogram> m_hitTypeLatencyHist;
|
209 Stats::Histogram m_hitLatencyHist; 210 std::vector<Stats::Histogram *> m_hitTypeLatencyHist; |
211 212 //! Histograms for profiling the latencies for requests that 213 //! did not required external messages.
|
207 std::vector<Histogram> m_hitMachLatencyHist;
208 std::vector< std::vector<Histogram> > m_hitTypeMachLatencyHist;
|
214 std::vector<Stats::Histogram *> m_hitMachLatencyHist; 215 std::vector< std::vector<Stats::Histogram *> > m_hitTypeMachLatencyHist; |
216 217 //! Histogram for holding latency profile of all requests that 218 //! miss in the controller connected to this sequencer.
|
212 Histogram m_missLatencyHist;
213 std::vector<Histogram> m_missTypeLatencyHist;
|
219 Stats::Histogram m_missLatencyHist; 220 std::vector<Stats::Histogram *> m_missTypeLatencyHist; |
221 222 //! Histograms for profiling the latencies for requests that 223 //! required external messages.
|
217 std::vector<Histogram> m_missMachLatencyHist;
218 std::vector< std::vector<Histogram> > m_missTypeMachLatencyHist;
|
224 std::vector<Stats::Histogram *> m_missMachLatencyHist; 225 std::vector< std::vector<Stats::Histogram *> > m_missTypeMachLatencyHist; |
226 227 //! Histograms for recording the breakdown of miss latency
|
221 std::vector<Histogram> m_IssueToInitialDelayHist;
222 std::vector<Histogram> m_InitialToForwardDelayHist;
223 std::vector<Histogram> m_ForwardToFirstResponseDelayHist;
224 std::vector<Histogram> m_FirstResponseToCompletionDelayHist;
225 std::vector<uint64_t> m_IncompleteTimes;
|
228 std::vector<Stats::Histogram *> m_IssueToInitialDelayHist; 229 std::vector<Stats::Histogram *> m_InitialToForwardDelayHist; 230 std::vector<Stats::Histogram *> m_ForwardToFirstResponseDelayHist; 231 std::vector<Stats::Histogram *> m_FirstResponseToCompletionDelayHist; 232 std::vector<Stats::Counter> m_IncompleteTimes; |
233 234 235 class SequencerWakeupEvent : public Event 236 { 237 private: 238 Sequencer *m_sequencer_ptr; 239 240 public: 241 SequencerWakeupEvent(Sequencer *_seq) : m_sequencer_ptr(_seq) {} 242 void process() { m_sequencer_ptr->wakeup(); } 243 const char *description() const { return "Sequencer deadlock check"; } 244 }; 245 246 SequencerWakeupEvent deadlockCheckEvent; 247}; 248 249inline std::ostream& 250operator<<(std::ostream& out, const Sequencer& obj) 251{ 252 obj.print(out); 253 out << std::flush; 254 return out; 255} 256 257#endif // __MEM_RUBY_SYSTEM_SEQUENCER_HH__
|