1 2/* 3 * Copyright (c) 1999-2008 Mark D. Hill and David A. Wood 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions are 8 * met: redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer; 10 * redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution; 13 * neither the name of the copyright holders nor the names of its 14 * contributors may be used to endorse or promote products derived from 15 * this software without specific prior written permission. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 18 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 19 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 20 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 21 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 22 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 23 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 24 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 25 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 26 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 27 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 28 */ 29 30/* 31 * $Id: Sequencer.hh 1.70 2006/09/27 14:56:41-05:00 bobba@s1-01.cs.wisc.edu $ 32 * 33 * Description: 34 * 35 */ 36 37#ifndef SEQUENCER_H 38#define SEQUENCER_H 39 40#include "mem/ruby/common/Global.hh" 41#include "mem/ruby/config/RubyConfig.hh" 42#include "mem/ruby/common/Consumer.hh" 43#include "mem/protocol/CacheRequestType.hh" 44#include "mem/protocol/AccessModeType.hh" 45#include "mem/protocol/GenericMachineType.hh" 46#include "mem/protocol/PrefetchBit.hh"
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47#include "mem/ruby/system/RubyPort.hh" |
48#include "mem/gems_common/Map.hh"
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49#include "mem/ruby/common/Address.hh" |
50 51class DataBlock;
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50class AbstractChip;
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52class CacheMsg;
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52class Address;
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53class MachineID;
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54class Packet;
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54class CacheMemory; 55class AbstractController; |
56
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56class Sequencer : public Consumer {
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57struct SequencerRequest { 58 RubyRequest ruby_request; 59 int64_t id; 60 Time issue_time; 61 62 SequencerRequest(const RubyRequest & _ruby_request, int64_t _id, Time _issue_time) 63 : ruby_request(_ruby_request), id(_id), issue_time(_issue_time) 64 {} 65}; 66 67class Sequencer : public Consumer, public RubyPort { |
68public: 69 // Constructors
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59 Sequencer(AbstractChip* chip_ptr, int version);
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70 Sequencer(const string & name); 71 void init(const vector<string> & argv); |
72 73 // Destructor 74 ~Sequencer(); 75 76 // Public Methods 77 void wakeup(); // Used only for deadlock detection 78
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67 static void printConfig(ostream& out);
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79 void printConfig(ostream& out) const; |
80
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69 // returns total number of outstanding request (includes prefetches)
70 int getNumberOutstanding();
71 // return only total number of outstanding demand requests
72 int getNumberOutstandingDemand();
73 // return only total number of outstanding prefetch requests
74 int getNumberOutstandingPrefetch();
75
76 // remove load/store request from queue
77 void removeLoadRequest(const Address & addr, int thread);
78 void removeStoreRequest(const Address & addr, int thread);
79
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81 void printProgress(ostream& out) const; 82
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82 // returns a pointer to the request in the request tables
83 CacheMsg & getReadRequest( const Address & addr, int thread );
84 CacheMsg & getWriteRequest( const Address & addr, int thread );
85
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83 void writeCallback(const Address& address, DataBlock& data); 84 void readCallback(const Address& address, DataBlock& data);
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88 void writeCallback(const Address& address);
89 void readCallback(const Address& address);
90 void writeCallback(const Address& address, DataBlock& data, GenericMachineType respondingMach, PrefetchBit pf, int thread);
91 void readCallback(const Address& address, DataBlock& data, GenericMachineType respondingMach, PrefetchBit pf, int thread);
92 void writeCallback(const Address& address, DataBlock& data, GenericMachineType respondingMach, int thread);
93 void readCallback(const Address& address, DataBlock& data, GenericMachineType respondingMach, int thread);
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85
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95 // returns the thread ID of the request
96 int getRequestThreadID(const Address & addr);
97 // returns the physical address of the request
98 Address getRequestPhysicalAddress(const Address & lineaddr);
99 // returns whether a request is a prefetch request
100 bool isPrefetchRequest(const Address & lineaddr);
101
102 //notifies driver of debug print
103 void printDebug();
104
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86 // called by Tester or Simics
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106 void makeRequest(Packet* pkt);
107 bool doRequest(const CacheMsg& request);
108 void issueRequest(const CacheMsg& request);
109 bool isReady(const Packet* pkt) const;
110 bool isReady(const CacheMsg& request) const; // depricate this function
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87 int64_t makeRequest(const RubyRequest & request); 88 bool isReady(const RubyRequest& request) const; |
89 bool empty() const;
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112 void resetRequestTime(const Address& addr, int thread);
113 Address getLogicalAddressOfRequest(Address address, int thread);
114 AccessModeType getAccessModeOfRequest(Address address, int thread);
115 //uint64 getSequenceNumberOfRequest(Address addr, int thread);
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90 91 void print(ostream& out) const; 92 void checkCoherence(const Address& address); 93
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120 bool getRubyMemoryValue(const Address& addr, char* value, unsigned int size_in_bytes);
121 bool setRubyMemoryValue(const Address& addr, char *value, unsigned int size_in_bytes);
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94 // bool getRubyMemoryValue(const Address& addr, char* value, unsigned int size_in_bytes); 95 // bool setRubyMemoryValue(const Address& addr, char *value, unsigned int size_in_bytes); |
96
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123 void removeRequest(const CacheMsg& request);
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97 void removeRequest(SequencerRequest* request); |
98private: 99 // Private Methods 100 bool tryCacheAccess(const Address& addr, CacheRequestType type, const Address& pc, AccessModeType access_mode, int size, DataBlock*& data_ptr);
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127 // void conflictCallback(const CacheMsg& request, GenericMachineType respondingMach, int thread);
128 void hitCallback(const CacheMsg& request, DataBlock& data, GenericMachineType respondingMach, int thread);
129 bool insertRequest(const CacheMsg& request);
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101 void issueRequest(const RubyRequest& request); |
102
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103 void hitCallback(SequencerRequest* request, DataBlock& data); 104 bool insertRequest(SequencerRequest* request); |
105
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106 |
107 // Private copy constructor and assignment operator 108 Sequencer(const Sequencer& obj); 109 Sequencer& operator=(const Sequencer& obj); 110
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136 // Data Members (m_ prefix)
137 AbstractChip* m_chip_ptr;
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111private: 112 int m_max_outstanding_requests; 113 int m_deadlock_threshold; |
114
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115 AbstractController* m_controller; 116 MessageBuffer* m_mandatory_q_ptr; 117 CacheMemory* m_dataCache_ptr; 118 CacheMemory* m_instCache_ptr; 119 |
120 // indicates what processor on the chip this sequencer is associated with 121 int m_version;
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122 int m_controller_type; |
123
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142 // One request table per SMT thread
143 Map<Address, CacheMsg>** m_writeRequestTable_ptr;
144 Map<Address, CacheMsg>** m_readRequestTable_ptr;
145
146 Map<Address, Packet*>* m_packetTable_ptr;
147
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124 Map<Address, SequencerRequest*> m_writeRequestTable; 125 Map<Address, SequencerRequest*> m_readRequestTable; |
126 // Global outstanding request count, across all request tables 127 int m_outstanding_count; 128 bool m_deadlock_check_scheduled; 129 130}; 131 132// Output operator declaration 133ostream& operator<<(ostream& out, const Sequencer& obj); 134 135// ******************* Definitions ******************* 136 137// Output operator definition 138extern inline 139ostream& operator<<(ostream& out, const Sequencer& obj) 140{ 141 obj.print(out); 142 out << flush; 143 return out; 144} 145 146#endif //SEQUENCER_H 147
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