1 2/* 3 * Copyright (c) 1999-2008 Mark D. Hill and David A. Wood 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions are 8 * met: redistributions of source code must retain the above copyright --- 30 unchanged lines hidden (view full) --- 39 40#include "mem/ruby/common/Global.hh" 41#include "mem/ruby/config/RubyConfig.hh" 42#include "mem/ruby/common/Consumer.hh" 43#include "mem/protocol/CacheRequestType.hh" 44#include "mem/protocol/AccessModeType.hh" 45#include "mem/protocol/GenericMachineType.hh" 46#include "mem/protocol/PrefetchBit.hh" |
47#include "mem/ruby/system/RubyPort.hh" |
48#include "mem/gems_common/Map.hh" |
49#include "mem/ruby/common/Address.hh" |
50 51class DataBlock; |
52class CacheMsg; |
53class MachineID; |
54class CacheMemory; 55class AbstractController; |
56 |
57struct SequencerRequest { 58 RubyRequest ruby_request; 59 int64_t id; 60 Time issue_time; 61 62 SequencerRequest(const RubyRequest & _ruby_request, int64_t _id, Time _issue_time) 63 : ruby_request(_ruby_request), id(_id), issue_time(_issue_time) 64 {} 65}; 66 67class Sequencer : public Consumer, public RubyPort { |
68public: 69 // Constructors |
70 Sequencer(const string & name); 71 void init(const vector<string> & argv); |
72 73 // Destructor 74 ~Sequencer(); 75 76 // Public Methods 77 void wakeup(); // Used only for deadlock detection 78 |
79 void printConfig(ostream& out) const; |
80 |
81 void printProgress(ostream& out) const; 82 |
83 void writeCallback(const Address& address, DataBlock& data); 84 void readCallback(const Address& address, DataBlock& data); |
85 |
86 // called by Tester or Simics |
87 int64_t makeRequest(const RubyRequest & request); 88 bool isReady(const RubyRequest& request) const; |
89 bool empty() const; |
90 91 void print(ostream& out) const; 92 void checkCoherence(const Address& address); 93 |
94 // bool getRubyMemoryValue(const Address& addr, char* value, unsigned int size_in_bytes); 95 // bool setRubyMemoryValue(const Address& addr, char *value, unsigned int size_in_bytes); |
96 |
97 void removeRequest(SequencerRequest* request); |
98private: 99 // Private Methods 100 bool tryCacheAccess(const Address& addr, CacheRequestType type, const Address& pc, AccessModeType access_mode, int size, DataBlock*& data_ptr); |
101 void issueRequest(const RubyRequest& request); |
102 |
103 void hitCallback(SequencerRequest* request, DataBlock& data); 104 bool insertRequest(SequencerRequest* request); |
105 |
106 |
107 // Private copy constructor and assignment operator 108 Sequencer(const Sequencer& obj); 109 Sequencer& operator=(const Sequencer& obj); 110 |
111private: 112 int m_max_outstanding_requests; 113 int m_deadlock_threshold; |
114 |
115 AbstractController* m_controller; 116 MessageBuffer* m_mandatory_q_ptr; 117 CacheMemory* m_dataCache_ptr; 118 CacheMemory* m_instCache_ptr; 119 |
120 // indicates what processor on the chip this sequencer is associated with 121 int m_version; |
122 int m_controller_type; |
123 |
124 Map<Address, SequencerRequest*> m_writeRequestTable; 125 Map<Address, SequencerRequest*> m_readRequestTable; |
126 // Global outstanding request count, across all request tables 127 int m_outstanding_count; 128 bool m_deadlock_check_scheduled; 129 130}; 131 132// Output operator declaration 133ostream& operator<<(ostream& out, const Sequencer& obj); --- 14 unchanged lines hidden --- |