1 2/* 3 * Copyright (c) 1999-2008 Mark D. Hill and David A. Wood 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions are 8 * met: redistributions of source code must retain the above copyright --- 31 unchanged lines hidden (view full) --- 40#include "Global.hh" 41#include "RubyConfig.hh" 42#include "Consumer.hh" 43#include "CacheRequestType.hh" 44#include "AccessModeType.hh" 45#include "GenericMachineType.hh" 46#include "PrefetchBit.hh" 47#include "Map.hh" |
48#include "packet.hh" |
49 50class DataBlock; 51class AbstractChip; 52class CacheMsg; 53class Address; 54class MachineID; 55 56class Sequencer : public Consumer { --- 47 unchanged lines hidden (view full) --- 104 Address getRequestPhysicalAddress(const Address & lineaddr); 105 // returns whether a request is a prefetch request 106 bool isPrefetchRequest(const Address & lineaddr); 107 108 //notifies driver of debug print 109 void printDebug(); 110 111 // called by Tester or Simics |
112 void makeRequest(const Packet* pkt, void* data); 113 void makeRequest(const CacheMsg& request); // depricate this function |
114 bool doRequest(const CacheMsg& request); 115 void issueRequest(const CacheMsg& request); |
116 bool isReady(const Packet* pkt) const; 117 bool isReady(const CacheMsg& request) const; // depricate this function |
118 bool empty() const; 119 void resetRequestTime(const Address& addr, int thread); 120 Address getLogicalAddressOfRequest(Address address, int thread); 121 AccessModeType getAccessModeOfRequest(Address address, int thread); 122 //uint64 getSequenceNumberOfRequest(Address addr, int thread); 123 124 void print(ostream& out) const; 125 void checkCoherence(const Address& address); --- 48 unchanged lines hidden --- |