1/* 2 * Copyright (c) 1999-2008 Mark D. Hill and David A. Wood 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; --- 166 unchanged lines hidden (view full) --- 175 176 private: 177 int m_max_outstanding_requests; 178 Cycles m_deadlock_threshold; 179 180 CacheMemory* m_dataCache_ptr; 181 CacheMemory* m_instCache_ptr; 182 |
183 // The cache access latency for top-level caches (L0/L1). These are 184 // currently assessed at the beginning of each memory access through the 185 // sequencer. 186 // TODO: Migrate these latencies into top-level cache controllers. 187 Cycles m_data_cache_hit_latency; 188 Cycles m_inst_cache_hit_latency; 189 |
190 typedef m5::hash_map<Address, SequencerRequest*> RequestTable; 191 RequestTable m_writeRequestTable; 192 RequestTable m_readRequestTable; 193 // Global outstanding request count, across all request tables 194 int m_outstanding_count; 195 bool m_deadlock_check_scheduled; 196 197 //! Counters for recording aliasing information. --- 65 unchanged lines hidden --- |