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> #include "mem/ruby/system/RubyPort.hh"
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> #include "mem/ruby/common/Address.hh"
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< class AbstractChip;
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< class Address;
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< class Packet;
---
> class CacheMemory;
> class AbstractController;
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< class Sequencer : public Consumer {
---
> struct SequencerRequest {
> RubyRequest ruby_request;
> int64_t id;
> Time issue_time;
>
> SequencerRequest(const RubyRequest & _ruby_request, int64_t _id, Time _issue_time)
> : ruby_request(_ruby_request), id(_id), issue_time(_issue_time)
> {}
> };
>
> class Sequencer : public Consumer, public RubyPort {
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< Sequencer(AbstractChip* chip_ptr, int version);
---
> Sequencer(const string & name);
> void init(const vector<string> & argv);
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< static void printConfig(ostream& out);
---
> void printConfig(ostream& out) const;
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< // returns total number of outstanding request (includes prefetches)
< int getNumberOutstanding();
< // return only total number of outstanding demand requests
< int getNumberOutstandingDemand();
< // return only total number of outstanding prefetch requests
< int getNumberOutstandingPrefetch();
<
< // remove load/store request from queue
< void removeLoadRequest(const Address & addr, int thread);
< void removeStoreRequest(const Address & addr, int thread);
<
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< // returns a pointer to the request in the request tables
< CacheMsg & getReadRequest( const Address & addr, int thread );
< CacheMsg & getWriteRequest( const Address & addr, int thread );
<
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< void writeCallback(const Address& address);
< void readCallback(const Address& address);
< void writeCallback(const Address& address, DataBlock& data, GenericMachineType respondingMach, PrefetchBit pf, int thread);
< void readCallback(const Address& address, DataBlock& data, GenericMachineType respondingMach, PrefetchBit pf, int thread);
< void writeCallback(const Address& address, DataBlock& data, GenericMachineType respondingMach, int thread);
< void readCallback(const Address& address, DataBlock& data, GenericMachineType respondingMach, int thread);
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< // returns the thread ID of the request
< int getRequestThreadID(const Address & addr);
< // returns the physical address of the request
< Address getRequestPhysicalAddress(const Address & lineaddr);
< // returns whether a request is a prefetch request
< bool isPrefetchRequest(const Address & lineaddr);
<
< //notifies driver of debug print
< void printDebug();
<
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< void makeRequest(Packet* pkt);
< bool doRequest(const CacheMsg& request);
< void issueRequest(const CacheMsg& request);
< bool isReady(const Packet* pkt) const;
< bool isReady(const CacheMsg& request) const; // depricate this function
---
> int64_t makeRequest(const RubyRequest & request);
> bool isReady(const RubyRequest& request) const;
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< void resetRequestTime(const Address& addr, int thread);
< Address getLogicalAddressOfRequest(Address address, int thread);
< AccessModeType getAccessModeOfRequest(Address address, int thread);
< //uint64 getSequenceNumberOfRequest(Address addr, int thread);
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< bool getRubyMemoryValue(const Address& addr, char* value, unsigned int size_in_bytes);
< bool setRubyMemoryValue(const Address& addr, char *value, unsigned int size_in_bytes);
---
> // bool getRubyMemoryValue(const Address& addr, char* value, unsigned int size_in_bytes);
> // bool setRubyMemoryValue(const Address& addr, char *value, unsigned int size_in_bytes);
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< void removeRequest(const CacheMsg& request);
---
> void removeRequest(SequencerRequest* request);
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< // void conflictCallback(const CacheMsg& request, GenericMachineType respondingMach, int thread);
< void hitCallback(const CacheMsg& request, DataBlock& data, GenericMachineType respondingMach, int thread);
< bool insertRequest(const CacheMsg& request);
---
> void issueRequest(const RubyRequest& request);
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> void hitCallback(SequencerRequest* request, DataBlock& data);
> bool insertRequest(SequencerRequest* request);
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>
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< // Data Members (m_ prefix)
< AbstractChip* m_chip_ptr;
---
> private:
> int m_max_outstanding_requests;
> int m_deadlock_threshold;
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> AbstractController* m_controller;
> MessageBuffer* m_mandatory_q_ptr;
> CacheMemory* m_dataCache_ptr;
> CacheMemory* m_instCache_ptr;
>
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> int m_controller_type;
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< // One request table per SMT thread
< Map<Address, CacheMsg>** m_writeRequestTable_ptr;
< Map<Address, CacheMsg>** m_readRequestTable_ptr;
<
< Map<Address, Packet*>* m_packetTable_ptr;
<
---
> Map<Address, SequencerRequest*> m_writeRequestTable;
> Map<Address, SequencerRequest*> m_readRequestTable;