1/*
2 * Copyright (c) 1999-2008 Mark D. Hill and David A. Wood
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
29#ifndef __MEM_RUBY_SYSTEM_SEQUENCER_HH__
30#define __MEM_RUBY_SYSTEM_SEQUENCER_HH__
31
32#include <iostream>
33
34#include "base/hashmap.hh"
| 1/*
2 * Copyright (c) 1999-2008 Mark D. Hill and David A. Wood
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
29#ifndef __MEM_RUBY_SYSTEM_SEQUENCER_HH__
30#define __MEM_RUBY_SYSTEM_SEQUENCER_HH__
31
32#include <iostream>
33
34#include "base/hashmap.hh"
|
35#include "mem/protocol/AccessModeType.hh"
| 35#include "mem/protocol/RubyAccessMode.hh"
|
36#include "mem/protocol/CacheRequestType.hh"
37#include "mem/protocol/GenericMachineType.hh"
38#include "mem/protocol/PrefetchBit.hh"
39#include "mem/ruby/common/Address.hh"
40#include "mem/ruby/common/Consumer.hh"
41#include "mem/ruby/common/Global.hh"
42#include "mem/ruby/system/RubyPort.hh"
43
44class DataBlock;
45class CacheMsg;
46class MachineID;
47class CacheMemory;
48
49class RubySequencerParams;
50
51struct SequencerRequest
52{
53 RubyRequest ruby_request;
54 Time issue_time;
55
56 SequencerRequest(const RubyRequest & _ruby_request, Time _issue_time)
57 : ruby_request(_ruby_request), issue_time(_issue_time)
58 {}
59};
60
61std::ostream& operator<<(std::ostream& out, const SequencerRequest& obj);
62
63class Sequencer : public RubyPort, public Consumer
64{
65 public:
66 typedef RubySequencerParams Params;
67 Sequencer(const Params *);
68 ~Sequencer();
69
70 // Public Methods
71 void wakeup(); // Used only for deadlock detection
72
73 void printConfig(std::ostream& out) const;
74
75 void printProgress(std::ostream& out) const;
76
77 void writeCallback(const Address& address, DataBlock& data);
78
79 void writeCallback(const Address& address,
80 GenericMachineType mach,
81 DataBlock& data);
82
83 void writeCallback(const Address& address,
84 GenericMachineType mach,
85 DataBlock& data,
86 Time initialRequestTime,
87 Time forwardRequestTime,
88 Time firstResponseTime);
89
90 void readCallback(const Address& address, DataBlock& data);
91
92 void readCallback(const Address& address,
93 GenericMachineType mach,
94 DataBlock& data);
95
96 void readCallback(const Address& address,
97 GenericMachineType mach,
98 DataBlock& data,
99 Time initialRequestTime,
100 Time forwardRequestTime,
101 Time firstResponseTime);
102
103 RequestStatus makeRequest(const RubyRequest & request);
104 RequestStatus getRequestStatus(const RubyRequest& request);
105 bool empty() const;
106
107 void print(std::ostream& out) const;
108 void printStats(std::ostream& out) const;
109 void checkCoherence(const Address& address);
110
111 void markRemoved();
112 void removeRequest(SequencerRequest* request);
113
114 private:
115 bool tryCacheAccess(const Address& addr, CacheRequestType type,
| 36#include "mem/protocol/CacheRequestType.hh"
37#include "mem/protocol/GenericMachineType.hh"
38#include "mem/protocol/PrefetchBit.hh"
39#include "mem/ruby/common/Address.hh"
40#include "mem/ruby/common/Consumer.hh"
41#include "mem/ruby/common/Global.hh"
42#include "mem/ruby/system/RubyPort.hh"
43
44class DataBlock;
45class CacheMsg;
46class MachineID;
47class CacheMemory;
48
49class RubySequencerParams;
50
51struct SequencerRequest
52{
53 RubyRequest ruby_request;
54 Time issue_time;
55
56 SequencerRequest(const RubyRequest & _ruby_request, Time _issue_time)
57 : ruby_request(_ruby_request), issue_time(_issue_time)
58 {}
59};
60
61std::ostream& operator<<(std::ostream& out, const SequencerRequest& obj);
62
63class Sequencer : public RubyPort, public Consumer
64{
65 public:
66 typedef RubySequencerParams Params;
67 Sequencer(const Params *);
68 ~Sequencer();
69
70 // Public Methods
71 void wakeup(); // Used only for deadlock detection
72
73 void printConfig(std::ostream& out) const;
74
75 void printProgress(std::ostream& out) const;
76
77 void writeCallback(const Address& address, DataBlock& data);
78
79 void writeCallback(const Address& address,
80 GenericMachineType mach,
81 DataBlock& data);
82
83 void writeCallback(const Address& address,
84 GenericMachineType mach,
85 DataBlock& data,
86 Time initialRequestTime,
87 Time forwardRequestTime,
88 Time firstResponseTime);
89
90 void readCallback(const Address& address, DataBlock& data);
91
92 void readCallback(const Address& address,
93 GenericMachineType mach,
94 DataBlock& data);
95
96 void readCallback(const Address& address,
97 GenericMachineType mach,
98 DataBlock& data,
99 Time initialRequestTime,
100 Time forwardRequestTime,
101 Time firstResponseTime);
102
103 RequestStatus makeRequest(const RubyRequest & request);
104 RequestStatus getRequestStatus(const RubyRequest& request);
105 bool empty() const;
106
107 void print(std::ostream& out) const;
108 void printStats(std::ostream& out) const;
109 void checkCoherence(const Address& address);
110
111 void markRemoved();
112 void removeRequest(SequencerRequest* request);
113
114 private:
115 bool tryCacheAccess(const Address& addr, CacheRequestType type,
|
116 const Address& pc, AccessModeType access_mode,
| 116 const Address& pc, RubyAccessMode access_mode,
|
117 int size, DataBlock*& data_ptr);
118 void issueRequest(const RubyRequest& request);
119
120 void hitCallback(SequencerRequest* request,
121 GenericMachineType mach,
122 DataBlock& data,
123 bool success,
124 Time initialRequestTime,
125 Time forwardRequestTime,
126 Time firstResponseTime);
127
128 bool insertRequest(SequencerRequest* request);
129
130 bool handleLlsc(const Address& address, SequencerRequest* request);
131
132 // Private copy constructor and assignment operator
133 Sequencer(const Sequencer& obj);
134 Sequencer& operator=(const Sequencer& obj);
135
136 private:
137 int m_max_outstanding_requests;
138 int m_deadlock_threshold;
139
140 CacheMemory* m_dataCache_ptr;
141 CacheMemory* m_instCache_ptr;
142
143 typedef m5::hash_map<Address, SequencerRequest*> RequestTable;
144 RequestTable m_writeRequestTable;
145 RequestTable m_readRequestTable;
146 // Global outstanding request count, across all request tables
147 int m_outstanding_count;
148 bool m_deadlock_check_scheduled;
149
150 int m_store_waiting_on_load_cycles;
151 int m_store_waiting_on_store_cycles;
152 int m_load_waiting_on_store_cycles;
153 int m_load_waiting_on_load_cycles;
154
155 class SequencerWakeupEvent : public Event
156 {
157 private:
158 Sequencer *m_sequencer_ptr;
159
160 public:
161 SequencerWakeupEvent(Sequencer *_seq) : m_sequencer_ptr(_seq) {}
162 void process() { m_sequencer_ptr->wakeup(); }
163 const char *description() const { return "Sequencer deadlock check"; }
164 };
165
166 SequencerWakeupEvent deadlockCheckEvent;
167};
168
169inline std::ostream&
170operator<<(std::ostream& out, const Sequencer& obj)
171{
172 obj.print(out);
173 out << std::flush;
174 return out;
175}
176
177#endif // __MEM_RUBY_SYSTEM_SEQUENCER_HH__
178
| 117 int size, DataBlock*& data_ptr);
118 void issueRequest(const RubyRequest& request);
119
120 void hitCallback(SequencerRequest* request,
121 GenericMachineType mach,
122 DataBlock& data,
123 bool success,
124 Time initialRequestTime,
125 Time forwardRequestTime,
126 Time firstResponseTime);
127
128 bool insertRequest(SequencerRequest* request);
129
130 bool handleLlsc(const Address& address, SequencerRequest* request);
131
132 // Private copy constructor and assignment operator
133 Sequencer(const Sequencer& obj);
134 Sequencer& operator=(const Sequencer& obj);
135
136 private:
137 int m_max_outstanding_requests;
138 int m_deadlock_threshold;
139
140 CacheMemory* m_dataCache_ptr;
141 CacheMemory* m_instCache_ptr;
142
143 typedef m5::hash_map<Address, SequencerRequest*> RequestTable;
144 RequestTable m_writeRequestTable;
145 RequestTable m_readRequestTable;
146 // Global outstanding request count, across all request tables
147 int m_outstanding_count;
148 bool m_deadlock_check_scheduled;
149
150 int m_store_waiting_on_load_cycles;
151 int m_store_waiting_on_store_cycles;
152 int m_load_waiting_on_store_cycles;
153 int m_load_waiting_on_load_cycles;
154
155 class SequencerWakeupEvent : public Event
156 {
157 private:
158 Sequencer *m_sequencer_ptr;
159
160 public:
161 SequencerWakeupEvent(Sequencer *_seq) : m_sequencer_ptr(_seq) {}
162 void process() { m_sequencer_ptr->wakeup(); }
163 const char *description() const { return "Sequencer deadlock check"; }
164 };
165
166 SequencerWakeupEvent deadlockCheckEvent;
167};
168
169inline std::ostream&
170operator<<(std::ostream& out, const Sequencer& obj)
171{
172 obj.print(out);
173 out << std::flush;
174 return out;
175}
176
177#endif // __MEM_RUBY_SYSTEM_SEQUENCER_HH__
178
|