1
2/*
3 * Copyright (c) 1999-2008 Mark D. Hill and David A. Wood
4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are
8 * met: redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer;
10 * redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution;
13 * neither the name of the copyright holders nor the names of its
14 * contributors may be used to endorse or promote products derived from
15 * this software without specific prior written permission.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
18 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
19 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
20 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
21 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
22 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
23 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
24 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
25 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
26 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
27 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28 */
29
30/*
31 * $Id: Sequencer.hh 1.70 2006/09/27 14:56:41-05:00 bobba@s1-01.cs.wisc.edu $
32 *
33 * Description:
34 *
35 */
36
37#ifndef SEQUENCER_H
38#define SEQUENCER_H
39
40#include "mem/ruby/common/Global.hh"
41#include "mem/ruby/common/Consumer.hh"
42#include "mem/protocol/CacheRequestType.hh"
43#include "mem/protocol/AccessModeType.hh"
44#include "mem/protocol/GenericMachineType.hh"
45#include "mem/protocol/PrefetchBit.hh"
46#include "mem/ruby/system/RubyPort.hh"
47#include "mem/gems_common/Map.hh"
48#include "mem/ruby/common/Address.hh"
49
50class DataBlock;
51class CacheMsg;
52class MachineID;
53class CacheMemory;
54class AbstractController;
55
56struct SequencerRequest {
57 RubyRequest ruby_request;
58 int64_t id;
59 Time issue_time;
60
61 SequencerRequest(const RubyRequest & _ruby_request, int64_t _id, Time _issue_time)
62 : ruby_request(_ruby_request), id(_id), issue_time(_issue_time)
63 {}
64};
65
66class Sequencer : public Consumer, public RubyPort {
67public:
68 // Constructors
69 Sequencer(const string & name);
70 void init(const vector<string> & argv);
71
72 // Destructor
73 ~Sequencer();
74
75 // Public Methods
76 void wakeup(); // Used only for deadlock detection
77
78 void printConfig(ostream& out) const;
79
80 void printProgress(ostream& out) const;
81
82 void writeCallback(const Address& address, DataBlock& data);
83 void readCallback(const Address& address, DataBlock& data);
84
85 // called by Tester or Simics
86 int64_t makeRequest(const RubyRequest & request);
87 int isReady(const RubyRequest& request);
88 bool empty() const;
89
90 void print(ostream& out) const;
91 void checkCoherence(const Address& address);
92
93 // bool getRubyMemoryValue(const Address& addr, char* value, unsigned int size_in_bytes);
94 // bool setRubyMemoryValue(const Address& addr, char *value, unsigned int size_in_bytes);
95
96 void removeRequest(SequencerRequest* request);
97private:
98 // Private Methods
99 bool tryCacheAccess(const Address& addr, CacheRequestType type, const Address& pc, AccessModeType access_mode, int size, DataBlock*& data_ptr);
100 void issueRequest(const RubyRequest& request);
101
102 void hitCallback(SequencerRequest* request, DataBlock& data);
103 bool insertRequest(SequencerRequest* request);
104
105
106 // Private copy constructor and assignment operator
107 Sequencer(const Sequencer& obj);
108 Sequencer& operator=(const Sequencer& obj);
109
110private:
111 int m_max_outstanding_requests;
112 int m_deadlock_threshold;
113
114 AbstractController* m_controller;
115 MessageBuffer* m_mandatory_q_ptr;
116 CacheMemory* m_dataCache_ptr;
117 CacheMemory* m_instCache_ptr;
118
119 // indicates what processor on the chip this sequencer is associated with
120 int m_version;
121 int m_controller_type;
122
123 Map<Address, SequencerRequest*> m_writeRequestTable;
124 Map<Address, SequencerRequest*> m_readRequestTable;
125 // Global outstanding request count, across all request tables
126 int m_outstanding_count;
127 bool m_deadlock_check_scheduled;
| 1
2/*
3 * Copyright (c) 1999-2008 Mark D. Hill and David A. Wood
4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are
8 * met: redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer;
10 * redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution;
13 * neither the name of the copyright holders nor the names of its
14 * contributors may be used to endorse or promote products derived from
15 * this software without specific prior written permission.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
18 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
19 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
20 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
21 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
22 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
23 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
24 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
25 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
26 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
27 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28 */
29
30/*
31 * $Id: Sequencer.hh 1.70 2006/09/27 14:56:41-05:00 bobba@s1-01.cs.wisc.edu $
32 *
33 * Description:
34 *
35 */
36
37#ifndef SEQUENCER_H
38#define SEQUENCER_H
39
40#include "mem/ruby/common/Global.hh"
41#include "mem/ruby/common/Consumer.hh"
42#include "mem/protocol/CacheRequestType.hh"
43#include "mem/protocol/AccessModeType.hh"
44#include "mem/protocol/GenericMachineType.hh"
45#include "mem/protocol/PrefetchBit.hh"
46#include "mem/ruby/system/RubyPort.hh"
47#include "mem/gems_common/Map.hh"
48#include "mem/ruby/common/Address.hh"
49
50class DataBlock;
51class CacheMsg;
52class MachineID;
53class CacheMemory;
54class AbstractController;
55
56struct SequencerRequest {
57 RubyRequest ruby_request;
58 int64_t id;
59 Time issue_time;
60
61 SequencerRequest(const RubyRequest & _ruby_request, int64_t _id, Time _issue_time)
62 : ruby_request(_ruby_request), id(_id), issue_time(_issue_time)
63 {}
64};
65
66class Sequencer : public Consumer, public RubyPort {
67public:
68 // Constructors
69 Sequencer(const string & name);
70 void init(const vector<string> & argv);
71
72 // Destructor
73 ~Sequencer();
74
75 // Public Methods
76 void wakeup(); // Used only for deadlock detection
77
78 void printConfig(ostream& out) const;
79
80 void printProgress(ostream& out) const;
81
82 void writeCallback(const Address& address, DataBlock& data);
83 void readCallback(const Address& address, DataBlock& data);
84
85 // called by Tester or Simics
86 int64_t makeRequest(const RubyRequest & request);
87 int isReady(const RubyRequest& request);
88 bool empty() const;
89
90 void print(ostream& out) const;
91 void checkCoherence(const Address& address);
92
93 // bool getRubyMemoryValue(const Address& addr, char* value, unsigned int size_in_bytes);
94 // bool setRubyMemoryValue(const Address& addr, char *value, unsigned int size_in_bytes);
95
96 void removeRequest(SequencerRequest* request);
97private:
98 // Private Methods
99 bool tryCacheAccess(const Address& addr, CacheRequestType type, const Address& pc, AccessModeType access_mode, int size, DataBlock*& data_ptr);
100 void issueRequest(const RubyRequest& request);
101
102 void hitCallback(SequencerRequest* request, DataBlock& data);
103 bool insertRequest(SequencerRequest* request);
104
105
106 // Private copy constructor and assignment operator
107 Sequencer(const Sequencer& obj);
108 Sequencer& operator=(const Sequencer& obj);
109
110private:
111 int m_max_outstanding_requests;
112 int m_deadlock_threshold;
113
114 AbstractController* m_controller;
115 MessageBuffer* m_mandatory_q_ptr;
116 CacheMemory* m_dataCache_ptr;
117 CacheMemory* m_instCache_ptr;
118
119 // indicates what processor on the chip this sequencer is associated with
120 int m_version;
121 int m_controller_type;
122
123 Map<Address, SequencerRequest*> m_writeRequestTable;
124 Map<Address, SequencerRequest*> m_readRequestTable;
125 // Global outstanding request count, across all request tables
126 int m_outstanding_count;
127 bool m_deadlock_check_scheduled;
|