1
2/*
3 * Copyright (c) 1999-2008 Mark D. Hill and David A. Wood
4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are
8 * met: redistributions of source code must retain the above copyright

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46#include "mem/ruby/system/RubyPort.hh"
47#include "mem/gems_common/Map.hh"
48#include "mem/ruby/common/Address.hh"
49
50class DataBlock;
51class CacheMsg;
52class MachineID;
53class CacheMemory;
54class AbstractController;
55
56struct SequencerRequest {
57 RubyRequest ruby_request;
58 int64_t id;
59 Time issue_time;
60
61 SequencerRequest(const RubyRequest & _ruby_request, int64_t _id, Time _issue_time)
62 : ruby_request(_ruby_request), id(_id), issue_time(_issue_time)
63 {}
64};
65
66std::ostream& operator<<(std::ostream& out, const SequencerRequest& obj);
67
68class Sequencer : public Consumer, public RubyPort {
69public:
70 // Constructors
71 Sequencer(const string & name);
72 void init(const vector<string> & argv);
73
74 // Destructor
75 ~Sequencer();
76
77 // Public Methods
78 void wakeup(); // Used only for deadlock detection
79
80 void printConfig(ostream& out) const;

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109 // Private copy constructor and assignment operator
110 Sequencer(const Sequencer& obj);
111 Sequencer& operator=(const Sequencer& obj);
112
113private:
114 int m_max_outstanding_requests;
115 int m_deadlock_threshold;
116
117 AbstractController* m_controller;
118 MessageBuffer* m_mandatory_q_ptr;
119 CacheMemory* m_dataCache_ptr;
120 CacheMemory* m_instCache_ptr;
121
122 // indicates what processor on the chip this sequencer is associated with
123 int m_version;
124 int m_controller_type;
125
126 Map<Address, SequencerRequest*> m_writeRequestTable;
127 Map<Address, SequencerRequest*> m_readRequestTable;
128 // Global outstanding request count, across all request tables
129 int m_outstanding_count;
130 bool m_deadlock_check_scheduled;
131

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